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-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/romstage.h2
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c4
2 files changed, 0 insertions, 6 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index 4e95dadadf..b01f11059c 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -25,13 +25,11 @@
#include <fsp/car.h>
#include <fsp/util.h>
#include <soc/intel/common/mma.h>
-#include <soc/pei_wrapper.h>
#include <soc/pm.h> /* chip_power_state */
struct romstage_params {
uint32_t fsp_version;
struct chipset_power_state *power_state;
- struct pei_data *pei_data;
void *chipset_context;
/* Fast boot and S3 resume MRC data */
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 87fd1a4c01..433e16cf13 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -41,9 +41,7 @@
asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
{
void *top_of_stack;
- struct pei_data pei_data;
struct romstage_params params = {
- .pei_data = &pei_data,
.chipset_context = fih,
};
@@ -55,8 +53,6 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
- memset(&pei_data, 0, sizeof(pei_data));
-
/* Display parameters */
if (!CONFIG(NO_MMCONF_SUPPORT))
printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",