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-rw-r--r--src/cpu/intel/model_2065x/bootblock.c1
-rw-r--r--src/cpu/intel/model_206ax/bootblock.c1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
index ed528d1bdd..edc2996f05 100644
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ b/src/cpu/intel/model_2065x/bootblock.c
@@ -24,6 +24,7 @@
#include <cpu/intel/microcode/microcode.c>
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)
+#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/ibexpeak/pch.h>
#include "model_2065x.h"
#else
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index 670b09750e..90215a496d 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -28,6 +28,7 @@
IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/rcba.h>
#else
#error "CPU must be paired with Intel BD82X6X or C216 southbridge"
#endif