diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/model_10xxx/Kconfig | 33 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/fidvid.c | 23 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 19 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/Kconfig | 26 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/fidvid.c | 42 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/init_cpus.c | 22 |
6 files changed, 87 insertions, 78 deletions
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 3789fdebdf..5ec6b270c0 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -4,27 +4,50 @@ config CPU_AMD_MODEL_10XXX select SSE select SSE2 +if CPU_AMD_MODEL_10XXX config CPU_ADDR_BITS int default 48 - depends on CPU_AMD_MODEL_10XXX config DCACHE_RAM_BASE hex default 0xc4000 - depends on CPU_AMD_MODEL_10XXX config DCACHE_RAM_SIZE hex default 0x0c000 - depends on CPU_AMD_MODEL_10XXX config DCACHE_RAM_GLOBAL_VAR_SIZE hex default 0x04000 - depends on CPU_AMD_MODEL_10XXX config UDELAY_IO bool default n - depends on CPU_AMD_MODEL_10XXX + +config SET_FIDVID + bool + default y + +if SET_FIDVID +config SET_FIDVID_DEBUG + bool + default y + +config SET_FIDVID_STORE_AP_APICID_AT_FIRST + bool + default y + +config SET_FIDVID_CORE0_ONLY + bool + default n + +# 0: all cores +# 1: core 0 only +# 2: all but core 0 +config SET_FIDVID_CORE_RANGE + int + default 0 + +endif +endif diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 22295c5654..b1a064a869 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -17,31 +17,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID #include <northbridge/amd/amdht/AsPsDefs.h> -#define SET_FIDVID_DEBUG 1 - -// if we are tight of CAR stack, disable it -#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 - static inline void print_debug_fv(const char *str, u32 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -729,7 +724,7 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) } -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st { u32 num; // it could use 256 bytes for 64 node quad core system @@ -748,7 +743,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp) static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st ap_apicidx; u32 i; #endif @@ -806,20 +801,20 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8); print_debug_fv("BSP fid = ", fv.common_fid); -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && SET_FIDVID_CORE0_ONLY == 0 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY /* For all APs (We know the APIC ID of all APs even when the APIC ID is lifted) remote read from AP LAPIC_MSG_REG about max fid. Then calculate the common max fid that can be used for all APs and BSP */ ap_apicidx.num = 0; - for_each_ap(bsp_apicid, SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); #endif print_debug_fv("common_fid = ", fv.common_fid); diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 8f85bceb75..0498fea4d4 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -28,17 +28,6 @@ #include <cpu/x86/mtrr/earlymtrr.c> #include <northbridge/amd/amdfam10/raminit_amdmct.c> -//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID -#ifndef SET_FIDVID - #define SET_FIDVID 1 -#endif - -#ifndef SET_FIDVID_CORE0_ONLY - /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, - Need to do every AP to set common FID/VID */ - #define SET_FIDVID_CORE0_ONLY 0 -#endif - static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); @@ -166,7 +155,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) return result; } -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid); #endif @@ -338,8 +327,8 @@ static u32 init_cpus(u32 cpu_init_detectedx) update_microcode(cpuid_eax(1)); cpuSetAMDMSR(); -#if SET_FIDVID == 1 -#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) +#if CONFIG_SET_FIDVID +#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY // Run on all AP for proper FID/VID setup. if (id.coreid == 0) // only need set fid for core0 #endif @@ -928,7 +917,7 @@ static void finalize_node_setup(struct sys_info *sysinfo) cpuSetAMDPCI(i); } -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID // Prep each node for FID/VID setup. prep_fid_change(); #endif diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 139b96ad25..962b399e03 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -4,7 +4,31 @@ config CPU_AMD_MODEL_FXX select SSE select SSE2 +if CPU_AMD_MODEL_FXX config UDELAY_IO bool default n - depends on CPU_AMD_MODEL_FXX + +config SET_FIDVID + bool + default n + default y if K8_REV_F_SUPPORT + +if SET_FIDVID +config SET_FIDVID_DEBUG + bool + default n + +config SET_FIDVID_CORE0_ONLY + bool + default y + +config SET_FIDVID_ONE_BY_ONE + bool + default y + +config SET_FIDVID_STORE_AP_APICID_AT_FIRST + bool + default y +endif +endif diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index bfbc93d577..bbafde6662 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -1,10 +1,4 @@ -#if SET_FIDVID == 1 - -#define SET_FIDVID_DEBUG 0 - -#define SET_FIDVID_ONE_BY_ONE 1 - -#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 +#if CONFIG_SET_FIDVID #ifndef SB_VFSMAF #define SB_VFSMAF 1 @@ -14,21 +8,21 @@ static inline void print_debug_fv(const char *str, u32 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -70,7 +64,7 @@ static void enable_fid_change(void) } } -#if SET_FIDVID_ONE_BY_ONE == 0 +#if !CONFIG_SET_FIDVID_ONE_BY_ONE static unsigned set_fidvid_without_init(unsigned fidvid) { msr_t msr; @@ -276,7 +270,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) ldtstop_sb(); #endif -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG if (showmessage) { print_debug_fv_8("set_fidvid APICID = ", apicid); print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo); @@ -290,7 +284,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) } fid_cur = msr.lo & 0x3f; -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG if (showmessage) { print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo); } @@ -368,7 +362,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */ send |= (apicid << 24); /* ap apicid */ -#if SET_FIDVID_ONE_BY_ONE == 1 +#if CONFIG_SET_FIDVID_ONE_BY_ONE vid_cur = msr.hi & 0x3f; fid_cur = msr.lo & 0x3f; @@ -399,7 +393,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) } if (loop > 0) { -#if SET_FIDVID_ONE_BY_ONE == 1 +#if CONFIG_SET_FIDVID_ONE_BY_ONE readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP #else readback = set_fidvid_without_init(readback & 0xffff00); // this AP @@ -502,7 +496,7 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp) print_debug_fv("\treadback=", readback); } -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st { u32 num; unsigned apicid[16]; /* 8 way dual core need 16 */ @@ -524,7 +518,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) struct fidvid_st fv; -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st ap_apicidx; unsigned i; #endif @@ -551,16 +545,16 @@ static void init_fidvid_bsp(unsigned bsp_apicid) /* calculate the common max fid/vid that could be used for * all APs and BSP */ -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST ap_apicidx.num = 0; - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); #endif #if 0 @@ -587,7 +581,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) #endif -#if SET_FIDVID_ONE_BY_ONE == 1 +#if CONFIG_SET_FIDVID_ONE_BY_ONE /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); @@ -601,15 +595,15 @@ static void init_fidvid_bsp(unsigned bsp_apicid) fv.common_fidvid &= 0xffff00; /* set state 2 allow is in init_fidvid_bsp_stage2 */ -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); #endif -#if SET_FIDVID_ONE_BY_ONE == 0 +#if !CONFIG_SET_FIDVID_ONE_BY_ONE /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 5672a6e8f1..570cb4e585 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -2,22 +2,6 @@ #include "option_table.h" #endif -//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID -#ifndef SET_FIDVID -#if CONFIG_K8_REV_F_SUPPORT == 0 - #define SET_FIDVID 0 -#else - // for rev F, need to set FID to max - #define SET_FIDVID 1 -#endif - -#endif - -#ifndef SET_FIDVID_CORE0_ONLY - /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice */ - #define SET_FIDVID_CORE0_ONLY 1 -#endif - typedef void (*process_ap_t) (u32 apicid, void *gp); //core_range = 0 : all cores @@ -135,7 +119,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) #define LAPIC_MSG_REG 0x380 -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID static void init_fidvid_ap(u32 bsp_apicid, u32 apicid); #endif @@ -291,8 +275,8 @@ static u32 init_cpus(u32 cpu_init_detectedx) u32 timeout = 1; u32 loop = 100; -#if SET_FIDVID == 1 -#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) +#if CONFIG_SET_FIDVID +#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY if (id.coreid == 0) // only need set fid for core0 #endif init_fidvid_ap(bsp_apicid, apicid); |