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-rw-r--r--src/cpu/amd/model_fxx/model_fxx_init.c6
-rw-r--r--src/cpu/x86/lapic/lapic.c2
-rw-r--r--src/cpu/x86/lapic/lapic_cpu_init.c10
-rw-r--r--src/cpu/x86/mtrr/mtrr.c2
4 files changed, 10 insertions, 10 deletions
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index 7c13d7fe67..3bccfe0d83 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -231,7 +231,7 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
size = (limitk - basek) << 10;
addr = map_2M_page(basek >> 11);
if (addr == MAPPING_ERROR) {
- printk_err("Cannot map page: %x\n", basek >> 11);
+ printk_err("Cannot map page: %lx\n", basek >> 11);
return;
}
@@ -312,7 +312,7 @@ static void init_ecc_memory(unsigned node_id)
begink = CONFIG_LB_MEM_TOPK;
}
- printk_debug("Clearing memory %uK - %uK: ", begink, endk);
+ printk_debug("Clearing memory %luK - %luK: ", begink, endk);
/* Save the normal state */
save_mtrr_state(&mtrr_state);
@@ -465,7 +465,9 @@ static inline void k8_errata(void)
extern void model_fxx_update_microcode(unsigned cpu_deviceid);
int init_processor_name(void);
+#if CONFIG_USBDEBUG_DIRECT
static unsigned ehci_debug_addr;
+#endif
void model_fxx_init(device_t dev)
{
diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c
index 8c111e8d71..fc736c96d2 100644
--- a/src/cpu/x86/lapic/lapic.c
+++ b/src/cpu/x86/lapic/lapic.c
@@ -55,7 +55,7 @@ void setup_lapic(void)
LAPIC_DELIVERY_MODE_NMI)
);
- printk_debug(" apic_id: 0x%02x ", lapicid());
+ printk_debug(" apic_id: 0x%02lx ", lapicid());
#else /* !NEED_LLAPIC */
/* Only Pentium Pro and later have those MSR stuff */
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 0fd31d0382..4a879c561a 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -85,14 +85,14 @@ static int lapic_start_cpu(unsigned long apicid)
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
- printk_err("CPU %d: First apic write timed out. Disabling\n",
+ printk_err("CPU %ld: First apic write timed out. Disabling\n",
apicid);
// too bad.
- printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
+ printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
if (lapic_read(LAPIC_ESR)) {
printk_err("Try to reset ESR\n");
lapic_write_around(LAPIC_ESR, 0);
- printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
+ printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
}
return 0;
}
@@ -114,7 +114,7 @@ static int lapic_start_cpu(unsigned long apicid)
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
- printk_err("CPU %d: Second apic write timed out. Disabling\n",
+ printk_err("CPU %ld: Second apic write timed out. Disabling\n",
apicid);
// too bad.
return 0;
@@ -345,8 +345,6 @@ void stop_this_cpu(void)
/* C entry point of secondary cpus */
void secondary_cpu_init(void)
{
- unsigned long cpunum;
-
atomic_inc(&active_cpus);
#if SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 71bbee8eca..840f9d3909 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -241,7 +241,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
align = max_align;
}
sizek = 1 << align;
- printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\n",
+ printk_debug("Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
reg, range_startk >>10, sizek >> 10,
(type==MTRR_TYPE_UNCACHEABLE)?"UC":
((type==MTRR_TYPE_WRBACK)?"WB":"Other")