diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/dualcore/dualcore_id.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/microcode/microcode.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/apic_timer.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/update_microcode.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/quadcore/quadcore_id.c | 2 | ||||
| -rw-r--r-- | src/cpu/x86/smm/smmrelocate.S | 2 |
6 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 67beb94dd5..33355cd558 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -2,7 +2,7 @@ #include <arch/cpu.h> #include <cpu/amd/dualcore.h> -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #include <cpu/amd/model_fxx_msr.h> #endif diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 82bb8beda5..1649b8222b 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #include <stdint.h> #include <console/console.h> diff --git a/src/cpu/amd/model_10xxx/apic_timer.c b/src/cpu/amd/model_10xxx/apic_timer.c index d1c0538c1f..d961da795b 100644 --- a/src/cpu/amd/model_10xxx/apic_timer.c +++ b/src/cpu/amd/model_10xxx/apic_timer.c @@ -23,8 +23,8 @@ #include <cpu/x86/lapic.h> /* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (ROMCC). Don't use init_timer() and udelay is redirected - * to udelay_tsc(). + * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is + * redirected to udelay_tsc(). */ diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index ff38c65377..a24b83d42e 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -18,7 +18,7 @@ */ -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -29,7 +29,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ /* From the Revision Guide : * Equivalent Processor Table for AMD Family 10h Processors diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index c4eab24a80..52f5e63f79 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -20,7 +20,7 @@ #include <arch/cpu.h> #include <cpu/amd/quadcore.h> -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #include <cpu/amd/model_10xxx_msr.h> #endif diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 3d1d9d2664..fa94b88113 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -22,7 +22,7 @@ #include <arch/asm.h> // Make sure no stage 2 code is included: -#define __ROMCC__ +#define __PRE_RAM__ // FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? |