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-rw-r--r--src/cpu/intel/haswell/romstage.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 8196273195..0cef888b49 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -38,6 +38,9 @@
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#endif
+#if CONFIG_EC_GOOGLE_CHROMEEC
+#include <ec/google/chromeec/ec.h>
+#endif
#include "haswell.h"
#include "northbridge/intel/haswell/haswell.h"
#include "northbridge/intel/haswell/raminit.h"
@@ -216,6 +219,11 @@ void romstage_common(const struct romstage_params *params)
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ /* Ensure the EC is in the right mode for recovery */
+ google_chromeec_early_init();
+#endif
+
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);