diff options
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/model_lx/model_lx_init.c | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/src/cpu/amd/model_lx/model_lx_init.c b/src/cpu/amd/model_lx/model_lx_init.c index ac075eca59..9eee1833e9 100644 --- a/src/cpu/amd/model_lx/model_lx_init.c +++ b/src/cpu/amd/model_lx/model_lx_init.c @@ -5,7 +5,6 @@ #include <cpu/cpu.h> #include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> -#include <cpu/amd/lxdef.h> static void vsm_end_post_smi(void) { @@ -19,37 +18,10 @@ static void vsm_end_post_smi(void) static void model_lx_init(device_t dev) { - - msr_t msr; - printk_debug("model_lx_init\n"); /* Turn on caching if we haven't already */ - /* Instruction Memory Configuration register - * set EBE bit, required when L2 cache is enabled - */ - msr = rdmsr(CPU_IM_CONFIG); - msr.lo |= 0x400; - wrmsr(CPU_IM_CONFIG, msr); - - /* Data Memory Subsystem Configuration register - * set EVCTONRPL bit, required when L2 cache is enabled in victim mode - */ - msr = rdmsr(CPU_DM_CONFIG0); - msr.lo |= 0x4000; - wrmsr(CPU_DM_CONFIG0, msr); - - /* invalidate L2 cache */ - msr.hi = 0x00; - msr.lo = 0x10; - wrmsr(L2_CONFIG_MSR, msr); - - /* Enable L2 cache */ - msr.hi = 0x00; - msr.lo = 0x0f; - wrmsr(L2_CONFIG_MSR, msr); - x86_enable_cache(); /* Enable the local cpu apics */ |