diff options
Diffstat (limited to 'src/cpu/amd/car')
| -rw-r--r-- | src/cpu/amd/car/clear_init_ram.c | 23 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 12 |
2 files changed, 8 insertions, 27 deletions
diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c deleted file mode 100644 index 624e0fea83..0000000000 --- a/src/cpu/amd/car/clear_init_ram.c +++ /dev/null @@ -1,23 +0,0 @@ -/* by yhlu 6.2005 */ -/* be warned, this file will be used core 0/node 0 only */ - -static void __attribute__((noinline)) clear_init_ram(void) -{ - // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram - // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already - // so noline clear_init_ram - -#if CONFIG_HAVE_ACPI_RESUME == 1 - /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ - clear_memory( CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); -#else - clear_memory(0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE)); -#endif -} - -/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ -static void set_init_ram_access(void) -{ - set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); -} - diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 5c085cd6d8..10194b9659 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -3,8 +3,6 @@ */ #include "cpu/amd/car/disable_cache_as_ram.c" -#include "cpu/amd/car/clear_init_ram.c" - static inline void print_debug_pcar(const char *strval, uint32_t val) { printk_debug("%s%08x\r\n", strval, val); @@ -64,7 +62,8 @@ static void post_cache_as_ram(void) #error "You need to set CONFIG_RAMTOP greater than 1M" #endif - set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */ + /* So we can access RAM from [1M, CONFIG_RAMTOP) */ + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00); print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); @@ -94,7 +93,12 @@ static void post_cache_as_ram(void) disable_cache_as_ram_bsp(); print_debug("Clearing initial memory region: "); - clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP)) +#if CONFIG_HAVE_ACPI_RESUME == 1 + /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ + memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0); +#else + memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0); +#endif print_debug("Done\r\n"); // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); |