diff options
Diffstat (limited to 'src/arch/x86')
32 files changed, 92 insertions, 92 deletions
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 623a6df2e3..486f8e34ed 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1066,7 +1066,7 @@ void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length) header->checksum = acpi_checksum((void *)bert, header->length); } -#if IS_ENABLED(CONFIG_COMMON_FADT) +#if CONFIG(COMMON_FADT) void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header); @@ -1088,11 +1088,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; - if (IS_ENABLED(CONFIG_SYSTEM_TYPE_CONVERTIBLE) || - IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP)) + if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) || + CONFIG(SYSTEM_TYPE_LAPTOP)) fadt->preferred_pm_profile = PM_MOBILE; - else if (IS_ENABLED(CONFIG_SYSTEM_TYPE_DETACHABLE) || - IS_ENABLED(CONFIG_SYSTEM_TYPE_TABLET)) + else if (CONFIG(SYSTEM_TYPE_DETACHABLE) || + CONFIG(SYSTEM_TYPE_TABLET)) fadt->preferred_pm_profile = PM_TABLET; else fadt->preferred_pm_profile = PM_DESKTOP; @@ -1256,7 +1256,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, mcfg); } - if (IS_ENABLED(CONFIG_TPM1)) { + if (CONFIG(TPM1)) { printk(BIOS_DEBUG, "ACPI: * TCPA\n"); tcpa = (acpi_tcpa_t *) current; acpi_create_tcpa(tcpa); @@ -1267,7 +1267,7 @@ unsigned long write_acpi_tables(unsigned long start) } } - if (IS_ENABLED(CONFIG_TPM2)) { + if (CONFIG(TPM2)) { printk(BIOS_DEBUG, "ACPI: * TPM2\n"); tpm2 = (acpi_tpm2_t *) current; acpi_create_tpm2(tpm2); diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index c62d6f3688..c57ba48094 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -19,7 +19,7 @@ #include <arch/acpigen.h> #include <device/device.h> #include <device/path.h> -#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB) +#if CONFIG(GENERIC_GPIO_LIB) #include <gpio.h> #endif @@ -342,7 +342,7 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio) /* Pin Table, one word for each pin */ for (pin = 0; pin < gpio->pin_count; pin++) { uint16_t acpi_pin = gpio->pins[pin]; -#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB) +#if CONFIG(GENERIC_GPIO_LIB) acpi_pin = gpio_acpi_pin(acpi_pin); #endif acpigen_emit_word(acpi_pin); @@ -352,7 +352,7 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio) acpi_device_fill_from_len(resource_offset, start); /* Resource Source Name String */ -#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB) +#if CONFIG(GENERIC_GPIO_LIB) acpigen_emit_string(gpio->resource ? : gpio_acpi_path(gpio->pins[0])); #else acpigen_emit_string(gpio->resource); diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index e455b45612..4c573033da 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -82,7 +82,7 @@ static int backup_create_or_update(struct resume_backup *backup_mem, { uintptr_t top; - if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { + if (CONFIG(ACPI_HUGE_LOWMEM_BACKUP)) { base = CONFIG_RAMBASE; size = HIGH_MEMORY_SAVE; } @@ -169,7 +169,7 @@ void acpi_prepare_resume_backup(void) if (!acpi_s3_resume_allowed()) return; - if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) + if (CONFIG(RELOCATABLE_RAMSTAGE)) return; backup_create_or_update(NULL, (uintptr_t)_program, @@ -194,7 +194,7 @@ static void acpi_jump_to_wakeup(void *vector) return; } - if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + if (!CONFIG(RELOCATABLE_RAMSTAGE)) { struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); if (backup_mem && backup_mem->valid) { backup_mem->valid = 0; @@ -224,7 +224,7 @@ void __weak mainboard_suspend_resume(void) void acpi_resume(void *wake_vec) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { void *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS); /* Restore GNVS pointer in SMM if found */ diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 02f492cfaa..4ead9ea769 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -16,7 +16,7 @@ #include <rules.h> -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) /* * This path is for stages that are post bootblock when employing @@ -43,8 +43,8 @@ _start: sub %edi, %ecx rep stosl -#if ((ENV_VERSTAGE && IS_ENABLED(CONFIG_VERSTAGE_DEBUG_SPINLOOP)) \ - || (ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_DEBUG_SPINLOOP))) +#if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ + || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP))) /* Wait for a JTAG debugger to break in and set EBX non-zero */ xor %ebx, %ebx @@ -55,7 +55,7 @@ debug_spinloop: #endif andl $0xfffffff0, %esp -#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) +#if CONFIG(IDT_IN_EVERY_STAGE) call exception_init #endif call car_stage_entry @@ -75,7 +75,7 @@ car_stage_entry: #include <arch/x86/prologue.inc> #include <cpu/x86/32bit/entry32.inc> #include <cpu/x86/fpu_enable.inc> -#if IS_ENABLED(CONFIG_SSE) +#if CONFIG(SSE) #include <cpu/x86/sse_enable.inc> #endif diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index 5a9333413a..8ccd3e4629 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -17,7 +17,7 @@ #include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> #include <arch/x86/id.ld> -#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) +#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) #include <cpu/intel/fit/fit.ld> #endif diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 4eb36b2ce1..ea55096abd 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -32,7 +32,7 @@ #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> -#if IS_ENABLED(CONFIG_BOOTBLOCK_DEBUG_SPINLOOP) +#if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) /* Wait for a JTAG debugger to break in and set EBX non-zero */ xor %ebx, %ebx @@ -44,7 +44,7 @@ debug_spinloop: bootblock_protected_mode_entry: -#if !IS_ENABLED(CONFIG_USE_MARCH_586) +#if !CONFIG(USE_MARCH_586) /* MMX registers required here */ /* BIST result in eax */ @@ -57,12 +57,12 @@ bootblock_protected_mode_entry: movd %edx, %mm2 #endif -#if IS_ENABLED(CONFIG_SSE) +#if CONFIG(SSE) enable_sse: mov %cr4, %eax or $CR4_OSFXSR, %ax mov %eax, %cr4 -#endif /* IS_ENABLED(CONFIG_SSE) */ +#endif /* CONFIG(SSE) */ /* We're done. Now it's up to platform-specific code */ jmp bootblock_pre_c_entry diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S index bfcc1e61a9..02603e91e3 100644 --- a/src/arch/x86/bootblock_romcc.S +++ b/src/arch/x86/bootblock_romcc.S @@ -37,7 +37,7 @@ #include <arch/x86/timestamp.inc> -#if IS_ENABLED(CONFIG_SSE) +#if CONFIG(SSE) #include <cpu/x86/sse_enable.inc> #endif diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c index bf71bca4e6..fc041c8018 100644 --- a/src/arch/x86/bootblock_simple.c +++ b/src/arch/x86/bootblock_simple.c @@ -22,12 +22,12 @@ static void main(unsigned long bist) bootblock_mainboard_init(); sanitize_cmos(); -#if IS_ENABLED(CONFIG_CMOS_POST) +#if CONFIG(CMOS_POST) cmos_post_init(); #endif } -#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE) +#if CONFIG(VBOOT_SEPARATE_VERSTAGE) const char *target1 = "fallback/verstage"; #else const char *target1 = "fallback/romstage"; diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 86147ecdc7..32b848df9b 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -25,7 +25,7 @@ _stack: .space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE _estack: -#if IS_ENABLED(CONFIG_COOP_MULTITASKING) +#if CONFIG(COOP_MULTITASKING) .global thread_stacks thread_stacks: .space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS @@ -76,7 +76,7 @@ _start: movl $_estack, %esp andl $(~(CONFIG_STACK_SIZE-1)), %esp -#if IS_ENABLED(CONFIG_COOP_MULTITASKING) +#if CONFIG(COOP_MULTITASKING) /* Push the thread pointer. */ push $0 #endif @@ -93,7 +93,7 @@ _start: andl $0xFFFFFFF0, %esp -#if IS_ENABLED(CONFIG_GDB_WAIT) +#if CONFIG(GDB_WAIT) call gdb_hw_init call gdb_stub_breakpoint #endif @@ -104,7 +104,7 @@ _start: hlt jmp .Lhlt -#if IS_ENABLED(CONFIG_GDB_WAIT) +#if CONFIG(GDB_WAIT) .globl gdb_stub_breakpoint gdb_stub_breakpoint: diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index d6576f73c4..4637362060 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -19,7 +19,7 @@ . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { _car_region_start = . ; -#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) +#if CONFIG(PAGING_IN_CACHE_AS_RAM) /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB * aligned when using this option. */ _pagetables = . ; @@ -28,7 +28,7 @@ #endif /* Vboot work buffer only needs to be available when verified boot * starts in bootblock. */ -#if IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) +#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) VBOOT2_WORK(., 16K) #endif /* Vboot measured boot TCPA log measurements. @@ -38,7 +38,7 @@ /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) _car_stack_start = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; _car_stack_end = .; @@ -48,7 +48,7 @@ * multiple stages (romstage and verstage) have a consistent * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) -#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) +#if CONFIG(PAGING_IN_CACHE_AS_RAM) . = ALIGN(32); /* Page directory pointer table resides here. There are 4 8-byte entries * totalling 32 bytes that need to be 32-byte aligned. The reason the @@ -74,7 +74,7 @@ * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ _car_global_start = .; -#if IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) +#if CONFIG(NO_CAR_GLOBAL_MIGRATION) /* Allow global unitialized variables when CAR_GLOBALs are not used. */ *(.bss) *(.bss.*) @@ -89,15 +89,15 @@ _car_global_end = .; _car_relocatable_data_end = .; -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) && \ - !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && \ + !CONFIG(USE_NATIVE_RAMINIT) . = ABSOLUTE(0xff7e1000); _mrc_pool = .; . += 0x5000; _emrc_pool = .; #endif -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) _car_stack_start = .; _car_stack_end = _car_region_end; #endif @@ -113,7 +113,7 @@ .illegal_globals . : { *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) -#if !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) +#if !CONFIG(NO_CAR_GLOBAL_MIGRATION) *(.bss) *(.bss.*) *(.sbss) @@ -125,9 +125,9 @@ } _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); -#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM) +#if CONFIG(PAGING_IN_CACHE_AS_RAM) _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); #endif -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); #endif diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 73967e17f8..648633f070 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> #include <arch/acpi.h> -#if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP) +#if CONFIG(CBMEM_TOP_BACKUP) void *cbmem_top(void) { @@ -39,7 +39,7 @@ void *cbmem_top(void) /* Something went wrong, our high memory area got wiped */ void cbmem_fail_resume(void) { -#if !defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if !defined(__PRE_RAM__) && CONFIG(HAVE_ACPI_RESUME) /* ACPI resume needs to be cleared in the fail-to-recover case, but that * condition is only handled during ramstage. */ acpi_fail_wakeup(); diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index d070dd924a..80d4d0da4a 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -284,7 +284,7 @@ void lb_arch_add_records(struct lb_header *header) struct lb_tsc_info *tsc_info; /* Don't advertise a TSC rate unless it's constant. */ - if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)) + if (!CONFIG(TSC_CONSTANT_RATE)) return; freq_khz = tsc_freq_mhz() * 1000; @@ -302,7 +302,7 @@ void lb_arch_add_records(struct lb_header *header) void arch_bootstate_coreboot_exit(void) { /* APs are already parked by existing infrastructure. */ - if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) + if (!CONFIG(PARALLEL_MP_AP_WORK)) return; /* APs are waiting for work. Last thing to do is park them. */ diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 700eb84cd0..b00777a455 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -22,7 +22,7 @@ #include <stdint.h> #include <string.h> -#if IS_ENABLED(CONFIG_GDB_STUB) +#if CONFIG(GDB_STUB) /* BUFMAX defines the maximum number of characters in inbound/outbound buffers. * At least NUM_REGBYTES*2 are needed for register packets @@ -394,7 +394,7 @@ void x86_exception(struct eregs *info); void x86_exception(struct eregs *info) { -#if IS_ENABLED(CONFIG_GDB_STUB) +#if CONFIG(GDB_STUB) int signo; memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t)); gdb_stub_registers[PC] = info->eip; diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 735399b8b1..769a758b9d 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -61,7 +61,7 @@ _start: * 0x00: Number of variable MTRRs to clear */ -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) +#if CONFIG(SOC_SETS_MSRS) mov %esp, %ebp /* Need to align stack to 16 bytes at the call instruction. Therefore diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c index 83ab858e22..c9aec6d111 100644 --- a/src/arch/x86/gdt.c +++ b/src/arch/x86/gdt.c @@ -40,7 +40,7 @@ static void move_gdt(int is_recovery) struct gdtarg gdtarg; /* ramstage is already in high memory. No need to use a new gdt. */ - if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) + if (CONFIG(RELOCATABLE_RAMSTAGE)) return; newgdt = cbmem_find(CBMEM_ID_GDT); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 63f3045ee0..f4ed7440c5 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -32,7 +32,7 @@ * The type and enable fields are common in ACPI, but the * values themselves are hardware implementation defined. */ -#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES) +#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) #define SLP_EN (1 << 13) #define SLP_TYP_SHIFT 10 #define SLP_TYP (7 << SLP_TYP_SHIFT) @@ -41,7 +41,7 @@ #define SLP_TYP_S3 5 #define SLP_TYP_S4 6 #define SLP_TYP_S5 7 -#elif IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES) +#elif CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES) #define SLP_EN (1 << 13) #define SLP_TYP_SHIFT 10 #define SLP_TYP (7 << SLP_TYP_SHIFT) @@ -776,7 +776,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current); void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length); void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); -#if IS_ENABLED(CONFIG_COMMON_FADT) +#if CONFIG(COMMON_FADT) void acpi_fill_fadt(acpi_fadt_t *fadt); #endif @@ -885,8 +885,8 @@ enum { ACPI_S5, }; -#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES) \ - || IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES) +#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \ + || CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES) /* Given the provided PM1 control register return the ACPI sleep type. */ static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt) { @@ -909,7 +909,7 @@ int acpi_get_gpe(int gpe); static inline int acpi_s3_resume_allowed(void) { - return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); + return CONFIG(HAVE_ACPI_RESUME); } /* Return address in reserved memory where to backup low memory @@ -919,7 +919,7 @@ static inline int acpi_s3_resume_allowed(void) */ void *acpi_backup_container(uintptr_t base, size_t size); -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) #ifdef __PRE_RAM__ static inline int acpi_is_wakeup_s3(void) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 3ee5cea761..b40dd1bc9e 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -188,7 +188,7 @@ struct thread; struct cpu_info { struct device *cpu; unsigned int index; -#if IS_ENABLED(CONFIG_COOP_MULTITASKING) +#if CONFIG(COOP_MULTITASKING) struct thread *thread; #endif }; diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 2b74544d5c..9ea1537d81 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -19,7 +19,7 @@ #include <arch/symbols.h> #include <stdlib.h> -#if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) +#if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); #ifdef __clang__ @@ -100,6 +100,6 @@ static inline int car_active(void) { return 0; } #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) (var) = (val) -#endif /* ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) */ +#endif /* ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) */ #endif /* ARCH_EARLY_VARIABLES_H */ diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h index 08aedef797..d71d5a51f4 100644 --- a/src/arch/x86/include/arch/exception.h +++ b/src/arch/x86/include/arch/exception.h @@ -32,7 +32,7 @@ #include <arch/cpu.h> -#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE +#if CONFIG(IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE asmlinkage void exception_init(void); #else static inline void exception_init(void) { /* not implemented */ } diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h index 3373e8223b..086e5bc8f2 100644 --- a/src/arch/x86/include/arch/interrupt.h +++ b/src/arch/x86/include/arch/interrupt.h @@ -21,9 +21,9 @@ #include "registers.h" /* setup interrupt handlers for mainboard */ -#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) +#if CONFIG(PCI_OPTION_ROM_RUN_REALMODE) extern void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void)); -#elif IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) +#elif CONFIG(PCI_OPTION_ROM_RUN_YABEL) #include <device/oprom/yabel/biosemu.h> #else static inline void mainboard_interrupt_handlers(int intXX, diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 3e2129fa1a..017e661f14 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -21,7 +21,7 @@ static __always_inline unsigned int pci_io_encode_addr(pci_devfn_t dev, unsigned int where) { - if (IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)) { + if (CONFIG(PCI_IO_CFG_EXT)) { // seg == 0 return dev >> 4 | (where & 0xff) | ((where & 0xf00) << 16); } else { @@ -77,7 +77,7 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value) outl(value, 0xCFC); } -#if !IS_ENABLED(CONFIG_MMCONF_SUPPORT) +#if !CONFIG(MMCONF_SUPPORT) /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 1d3b90aa93..41275a8dc2 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -60,7 +60,7 @@ struct eregs { }; #endif // !ASSEMBLER -#if IS_ENABLED(CONFIG_COMPILER_LLVM_CLANG) +#if CONFIG(COMPILER_LLVM_CLANG) #define ADDR32(opcode) opcode #else #define ADDR32(opcode) addr32 opcode diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 183d726d19..f9186787af 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -15,9 +15,9 @@ #define ARCH_SMP_SPINLOCK_H #if !defined(__PRE_RAM__) \ - || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \ - || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \ - || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) + || CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \ + || CONFIG(HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \ + || CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) /* * Your basic SMP spinlocks, allowing only a single CPU anywhere diff --git a/src/arch/x86/include/cf9_reset.h b/src/arch/x86/include/cf9_reset.h index c0dcc92bd1..7b44e0f2a6 100644 --- a/src/arch/x86/include/cf9_reset.h +++ b/src/arch/x86/include/cf9_reset.h @@ -27,7 +27,7 @@ void do_system_reset(void); void do_full_reset(void); /* Called by functions below before reset. */ -#if IS_ENABLED(CONFIG_HAVE_CF9_RESET_PREPARE) +#if CONFIG(HAVE_CF9_RESET_PREPARE) void cf9_reset_prepare(void); #else static inline void cf9_reset_prepare(void) {} diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index a3969529ca..34ab202f71 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -103,7 +103,7 @@ static void load_vectors(void *ioapic_base) ioapic_interrupts = ioapic_interrupt_count(ioapic_base); - if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_FSB)) { + if (CONFIG(IOAPIC_INTERRUPTS_ON_FSB)) { /* * For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. @@ -111,7 +111,7 @@ static void load_vectors(void *ioapic_base) printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); - } else if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) { + } else if (CONFIG(IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) { printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 5831723466..8e073f25cf 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -62,7 +62,7 @@ SECTIONS #include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> #include <arch/x86/id.ld> -#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) +#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) #include <cpu/intel/fit/fit.ld> #endif #endif /* ENV_BOOTBLOCK */ diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c index b1dadc3e23..7d82507fd2 100644 --- a/src/arch/x86/pci_ops_conf1.c +++ b/src/arch/x86/pci_ops_conf1.c @@ -18,7 +18,7 @@ * Functions for accessing PCI configuration space with type 1 accesses */ -#if !IS_ENABLED(CONFIG_PCI_IO_CFG_EXT) +#if !CONFIG(PCI_IO_CFG_EXT) #define CONF_CMD(dev, where) (0x80000000 | ((dev)->bus->secondary << 16) | \ ((dev)->path.pci.devfn << 8) | (where & ~3)) #else diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index f705944658..194efb4ad2 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -198,9 +198,9 @@ unsigned long copy_pirq_routing_table(unsigned long addr, addr); memcpy((void *)addr, routing_table, routing_table->size); printk(BIOS_INFO, "done.\n"); - if (IS_ENABLED(CONFIG_DEBUG_PIRQ)) + if (CONFIG(DEBUG_PIRQ)) verify_copy_pirq_routing_table(addr, routing_table); - if (IS_ENABLED(CONFIG_PIRQ_ROUTE)) + if (CONFIG(PIRQ_ROUTE)) pirq_route_irqs(addr); return addr + routing_table->size; diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index a36b90058f..d62487ef88 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -106,7 +106,7 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf, void postcar_frame_add_romcache(struct postcar_frame *pcf, int type) { - if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) + if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) return; postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type); } @@ -151,7 +151,7 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) finalize_load(rsl.params, pcf->stack); - if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE)) + if (!CONFIG(NO_STAGE_CACHE)) stage_cache_add(STAGE_POSTCAR, prog); } @@ -162,7 +162,7 @@ void run_postcar_phase(struct postcar_frame *pcf) postcar_commit_mtrrs(pcf); - if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE) && + if (!CONFIG(NO_STAGE_CACHE) && romstage_handoff_is_resume()) { stage_cache_load_stage(STAGE_POSTCAR, &prog); /* This is here to allow platforms to pass different stack diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index fdf8ca1358..1d0ced16c9 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -30,7 +30,7 @@ #include <memory_info.h> #include <spd.h> #include <cbmem.h> -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -350,7 +350,7 @@ static int smbios_write_type0(unsigned long *current, int handle) t->length = len - 2; t->vendor = smbios_add_string(t->eos, "coreboot"); -#if !IS_ENABLED(CONFIG_CHROMEOS) +#if !CONFIG(CHROMEOS) t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); t->bios_version = smbios_add_string(t->eos, @@ -359,12 +359,12 @@ static int smbios_write_type0(unsigned long *current, int handle) #define SPACES \ " " t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) u32 version_offset = (u32)smbios_string_table_len(t->eos); #endif t->bios_version = smbios_add_string(t->eos, SPACES); -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) /* SMBIOS offsets start at 1 rather than 0 */ chromeos_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1); @@ -390,10 +390,10 @@ static int smbios_write_type0(unsigned long *current, int handle) BIOS_CHARACTERISTICS_SELECTABLE_BOOT | BIOS_CHARACTERISTICS_UPGRADEABLE; - if (IS_ENABLED(CONFIG_CARDBUS_PLUGIN_SUPPORT)) + if (CONFIG(CARDBUS_PLUGIN_SUPPORT)) t->bios_characteristics |= BIOS_CHARACTERISTICS_PC_CARD; - if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + if (CONFIG(HAVE_ACPI_TABLES)) t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI; t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET; @@ -402,7 +402,7 @@ static int smbios_write_type0(unsigned long *current, int handle) return len; } -#if !IS_ENABLED(CONFIG_SMBIOS_PROVIDED_BY_MOBO) +#if !CONFIG(SMBIOS_PROVIDED_BY_MOBO) const char *__weak smbios_mainboard_serial_number(void) { @@ -753,7 +753,7 @@ unsigned long smbios_write_tables(unsigned long current) handle++)); update_max(len, max_struct_size, smbios_write_type11(¤t, &handle)); - if (IS_ENABLED(CONFIG_ELOG)) + if (CONFIG(ELOG)) update_max(len, max_struct_size, elog_smbios_write_type15(¤t,handle++)); update_max(len, max_struct_size, smbios_write_type17(¤t, diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 5319c690f2..f17fb858b0 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -238,17 +238,17 @@ void arch_write_tables(uintptr_t coreboot_table) unsigned long rom_table_end = 0xf0000; /* This table must be between 0x0f0000 and 0x100000 */ - if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)) + if (CONFIG(GENERATE_PIRQ_TABLE)) rom_table_end = write_pirq_table(rom_table_end); /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ - if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) + if (CONFIG(GENERATE_MP_TABLE)) rom_table_end = write_mptable(rom_table_end); - if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + if (CONFIG(HAVE_ACPI_TABLES)) rom_table_end = write_acpi_table(rom_table_end); - if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)) + if (CONFIG(GENERATE_SMBIOS_TABLES)) rom_table_end = write_smbios_table(rom_table_end); sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table); diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index b5257c4c7e..5b48c23be2 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -24,7 +24,7 @@ uint64_t timestamp_get(void) int timestamp_tick_freq_mhz(void) { /* Chipsets that have a constant TSC provide this value correctly. */ - if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)) + if (CONFIG(TSC_CONSTANT_RATE)) return tsc_freq_mhz(); /* Filling tick_freq_mhz = 0 in timestamps-table will trigger |