diff options
Diffstat (limited to 'src/arch/mips/include')
| -rw-r--r-- | src/arch/mips/include/arch/cpu.h | 73 | ||||
| -rw-r--r-- | src/arch/mips/include/arch/mmu.h | 59 |
2 files changed, 132 insertions, 0 deletions
diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h index 4f4c376eee..957e427e73 100644 --- a/src/arch/mips/include/arch/cpu.h +++ b/src/arch/mips/include/arch/cpu.h @@ -79,13 +79,86 @@ do { \ } while (0) /* Shortcuts to access various internal registers, keep adding as needed. */ +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, (val)) + +#define read_c0_entrylo0() __read_32bit_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, (val)) + +#define read_c0_entrylo1() __read_32bit_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, (val)) + +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, (val)) + +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, (val)) + #define read_c0_count() __read_32bit_c0_register($9, 0) #define write_c0_count(val) __write_32bit_c0_register($9, 0, (val)) +#define read_c0_entryhi() __read_32bit_c0_register($10, 0) +#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, (val)) + #define read_c0_cause() __read_32bit_c0_register($13, 0) #define write_c0_cause(val) __write_32bit_c0_register($13, 0, (val)) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, (val)) + +#define C0_ENTRYLO_PFN_SHIFT 6 +#define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */ +#define C0_ENTRYLO_D (0x1 << 2) /* Writeable */ +#define C0_ENTRYLO_V (0x1 << 1) /* Valid */ +#define C0_ENTRYLO_G (0x1 << 0) /* Global */ + +#define C0_PAGEMASK_SHIFT 13 +#define C0_PAGEMASK_MASK 0xffff + +#define C0_WIRED_MASK 0x3f + #define C0_CAUSE_DC (1 << 27) + +#define C0_CONFIG1_MMUSIZE_SHIFT 25 +#define C0_CONFIG1_MMUSIZE_MASK 0x3f + +/* Hazard handling */ +static inline void __nop(void) +{ + __asm__ __volatile__("nop"); +} + +static inline void __ssnop(void) +{ + __asm__ __volatile__("sll\t$0, $0, 1"); +} + +#define mtc0_tlbw_hazard() \ +do { \ + __nop(); \ + __nop(); \ +} while (0) + +#define tlbw_use_hazard() \ +do { \ + __nop(); \ + __nop(); \ + __nop(); \ +} while (0) + +#define tlb_probe_hazard() \ +do { \ + __nop(); \ + __nop(); \ + __nop(); \ +} while (0) + +#define back_to_back_c0_hazard() \ +do { \ + __ssnop(); \ + __ssnop(); \ + __ssnop(); \ +} while (0) /**************************************************************************/ #endif /* __MIPS_ARCH_CPU_H */ diff --git a/src/arch/mips/include/arch/mmu.h b/src/arch/mips/include/arch/mmu.h new file mode 100644 index 0000000000..27385f81e5 --- /dev/null +++ b/src/arch/mips/include/arch/mmu.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MIPS_ARCH_MMU_H +#define __MIPS_ARCH_MMU_H + +#include <arch/cpu.h> +#include <stddef.h> +#include <stdint.h> + +static inline void tlb_write_indexed(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwi\n\t" + ".set reorder"); +} + +static inline uint32_t get_max_pagesize(void) +{ + uint32_t max_pgsize; + + write_c0_pagemask(C0_PAGEMASK_MASK << C0_PAGEMASK_SHIFT); + back_to_back_c0_hazard(); + max_pgsize = (((read_c0_pagemask() >> C0_PAGEMASK_SHIFT) & + C0_PAGEMASK_MASK) + 1) * 4 * KiB; + + return max_pgsize; +} + +static inline uint32_t get_tlb_size(void) +{ + uint32_t tlbsize; + + tlbsize = ((read_c0_config1() >> C0_CONFIG1_MMUSIZE_SHIFT) & + C0_CONFIG1_MMUSIZE_MASK) + 1; + + return tlbsize; +} + +int identity_map(uint32_t start, size_t len); + +#endif /* __MIPS_ARCH_MMU_H */ |