diff options
Diffstat (limited to 'payloads/libpayload')
| -rw-r--r-- | payloads/libpayload/Kconfig | 5 | ||||
| -rw-r--r-- | payloads/libpayload/drivers/Makefile.inc | 2 | ||||
| -rw-r--r-- | payloads/libpayload/drivers/pcie_mediatek.c | 20 |
3 files changed, 27 insertions, 0 deletions
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 7540c674a2..2ad3c00206 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -413,6 +413,11 @@ config PCI_IO_OPS default y if ARCH_X86 default n +config PCIE_MEDIATEK + bool "Support for PCIe devices on MediaTek platforms" + depends on PCI && !PCI_IO_OPS + default n + config NVRAM bool "Support for reading/writing NVRAM bytes" depends on ARCH_X86 # for now diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index b2a91f6610..204760757b 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -36,6 +36,8 @@ else libc-$(CONFIG_LP_PCI) += pci_map_bus_ops.c endif +libc-$(CONFIG_LP_PCIE_MEDIATEK) += pcie_mediatek.c + libc-$(CONFIG_LP_SPEAKER) += speaker.c libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial/8250.c serial/serial.c diff --git a/payloads/libpayload/drivers/pcie_mediatek.c b/payloads/libpayload/drivers/pcie_mediatek.c new file mode 100644 index 0000000000..a953bd7fae --- /dev/null +++ b/payloads/libpayload/drivers/pcie_mediatek.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <libpayload.h> +#include <pci.h> + +#define PCIE_CFGNUM_REG 0x140 +#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) +#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) +#define PCIE_CFG_OFFSET_ADDR 0x1000 +#define PCIE_CFG_HEADER(bus, devfn) \ + (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn)) + +uintptr_t pci_map_bus(pcidev_t dev) +{ + u32 devfn = (PCI_SLOT(dev) << 3) | PCI_FUNC(dev); + u32 val = PCIE_CFG_HEADER(PCI_BUS(dev), devfn); + write32((void *)(lib_sysinfo.pcie_ctrl_base + PCIE_CFGNUM_REG), val); + + return lib_sysinfo.pcie_ctrl_base + PCIE_CFG_OFFSET_ADDR; +} |