diff options
| -rw-r--r-- | src/arch/armv7/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/arch/armv7/bootblock.inc | 12 | ||||
| -rw-r--r-- | src/arch/armv7/cpu.c | 42 | ||||
| -rw-r--r-- | src/arch/armv7/include/arch/cpu.h | 1 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5420/Kconfig | 22 |
5 files changed, 74 insertions, 4 deletions
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index a611b09da2..2188706e06 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -170,6 +170,7 @@ ramstage-y += exception_asm.S ramstage-y += div0.c #ramstage-y += interrupts.c ramstage-y += cache.c +ramstage-y += cpu.c ramstage-y += mmu.c ramstage-y += eabi_compat.c ramstage-y += boot.c diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index b2c993af32..c45259db6d 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -82,8 +82,15 @@ init_stack_loop: /* Set stackpointer in internal RAM to call board_init_f */ call_bootblock: ldr sp, .Stack /* Set up stack pointer */ - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ldr r0,=0x00000000 + /* + * The current design of cpu_info places the + * struct at the top of the stack. The number of + * words pushed must be at least as large as that + * struct. + */ + push {r0-r2} + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ /* * Use "bl" instead of "b" even though we do not intend to return. * "bl" gets compiled to "blx" if we're transitioning from ARM to @@ -104,5 +111,6 @@ wait_for_interrupt: .Stack: .word CONFIG_STACK_TOP .align 2 +/* create this size the same way we do in coreboot_ram.ld: top-bottom */ .Stack_size: - .word CONFIG_STACK_SIZE + .word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM diff --git a/src/arch/armv7/cpu.c b/src/arch/armv7/cpu.c new file mode 100644 index 0000000000..f90c759559 --- /dev/null +++ b/src/arch/armv7/cpu.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include <stdlib.h> +#include <arch/cpu.h> + +/* Return the cpu struct which is at the high memory address of the stack. + */ +struct cpu_info *cpu_info(void) +{ + uintptr_t addr = ALIGN((uintptr_t)__builtin_frame_address(0), + CONFIG_STACK_SIZE); + addr -= sizeof(struct cpu_info); + return (void *)addr; +} + diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h index ec37a969ce..df44a9244c 100644 --- a/src/arch/armv7/include/arch/cpu.h +++ b/src/arch/armv7/include/arch/cpu.h @@ -104,4 +104,5 @@ inline static void set_svc32_mode(void) asm volatile("msr cpsr_c, %0" :: "r"(0x13 | 0xc0)); } +struct cpu_info *cpu_info(void); #endif /* __ARCH_CPU_H__ */ diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index d3eafcba75..66679a000b 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -69,7 +69,17 @@ config ROMSTAGE_SIZE # at the top of IRAM for now. # # Stack grows downward, push operation stores register contents in -# consecutive memory locations ending just below SP +# consecutive memory locations ending just below SP. +# The setup in the exynos 5420 is a new one for coreboot. We have got +# the bootblock, romstage, and ramstage sharing the same stack space. +# The SRAM is always there and having a known-good stack memory +# makes for a more reliable setup. +# Thus, in this case: +# STACK_TOP: highest stack address in SRAM +# STACK_BOTTOM: lowest stack address in SRAM +# STACK_SIZE: as in standard coreboot usage, size of thread stacks in ramstage +# ROMSTAGE_STACK_SIZE: size of the single stack in romstage + config STACK_TOP hex default 0x02073000 @@ -78,10 +88,18 @@ config STACK_BOTTOM hex default 0x0206f000 -config STACK_SIZE +# The romstage stack must be large enough to contain the lzma buffer +config ROMSTAGE_STACK_SIZE hex default 0x4000 +# STACK_SIZE is for the ramstage core and thread stacks. +# It must be a power of 2, to make the cpu_info computation work, +# and cpu_info needs to work to make SMP startup and threads work. +config STACK_SIZE + hex + default 0x0800 + # TODO We may probably move this to board-specific implementation files instead # of KConfig values. config CBFS_CACHE_ADDRESS |