diff options
| -rw-r--r-- | src/soc/intel/meteorlake/chip.h | 24 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/chipset.cb | 4 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 6 |
3 files changed, 34 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index e860ba97e1..59b6a8b8a2 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -306,6 +306,30 @@ struct soc_intel_meteorlake_config { */ uint16_t fast_vmode_i_trip[NUM_VR_DOMAINS]; + /* + * Power state current threshold 1. + * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, + * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for + * SA, [3] through [5] are Reserved. + */ + uint16_t ps_cur_1_threshold[NUM_VR_DOMAINS]; + + /* + * Power state current threshold 2. + * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, + * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for + * SA, [3] through [5] are Reserved. + */ + uint16_t ps_cur_2_threshold[NUM_VR_DOMAINS]; + + /* + * Power state current threshold 3. + * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, + * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for + * SA, [3] through [5] are Reserved. + */ + uint16_t ps_cur_3_threshold[NUM_VR_DOMAINS]; + uint8_t PmTimerDisabled; /* * SerialIO device mode selection: diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 69d0df357d..865b3d0af7 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -17,6 +17,10 @@ chip soc/intel/meteorlake # Reduce the size of BasicMemoryTests to speed up the boot time. register "lower_basic_mem_test_size" = "true" + # The power state current threshold is defined in 1/4 A + # increments. A value of 400 = 100A. + register "ps_cur_2_threshold[VR_DOMAIN_SA]" = "40" # 10A + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 8f64d4fb3c..2c39bcd0f5 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -238,6 +238,12 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg, m_cfg->IccLimit[domain] = config->fast_vmode_i_trip[domain]; } } + if (config->ps_cur_1_threshold[domain]) + m_cfg->Psi1Threshold[domain] = config->ps_cur_1_threshold[domain]; + if (config->ps_cur_2_threshold[domain]) + m_cfg->Psi2Threshold[domain] = config->ps_cur_2_threshold[domain]; + if (config->ps_cur_3_threshold[domain]) + m_cfg->Psi3Threshold[domain] = config->ps_cur_3_threshold[domain]; } } |