diff options
| -rw-r--r-- | src/arch/arm/armv7/mmu.c | 4 | ||||
| -rw-r--r-- | src/arch/arm/include/armv7/arch/cache.h | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index d823c61f35..51b4860768 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -118,7 +118,7 @@ static void mmu_fill_table(pte_t *table, u32 start_idx, u32 end_idx, /* Invalidate the TLB entries. */ for (i = start_idx; i < end_idx; i++) - tlbimvaa(offset + (i << shift)); + tlbimva(offset + (i << shift)); dsb(); isb(); } @@ -152,7 +152,7 @@ static pte_t *mmu_create_subtable(pte_t *pgd_entry) *pgd_entry = (pte_t)(uintptr_t)table | ATTR_NEXTLEVEL; dccmvac((uintptr_t)pgd_entry); dsb(); - tlbimvaa(start_addr); + tlbimva(start_addr); dsb(); isb(); diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index 600ec46f91..e332c31663 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -73,10 +73,10 @@ static inline void tlbiall(void) asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory"); } -/* invalidate unified TLB by MVA, all ASID */ -static inline void tlbimvaa(unsigned long mva) +/* invalidate unified TLB by MVA and ASID */ +static inline void tlbimva(unsigned long mva) { - asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory"); + asm volatile ("mcr p15, 0, %0, c8, c7, 1" : : "r" (mva) : "memory"); } /* write data access control register (DACR) */ |