diff options
4 files changed, 30 insertions, 33 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c index 3d61a8209c..12c6feb398 100644 --- a/src/soc/intel/xeon_sp/cpx/hob_display.c +++ b/src/soc/intel/xeon_sp/cpx/hob_display.c @@ -133,22 +133,16 @@ static void soc_display_iio_universal_data_hob(const IIO_UDS *hob) printk(BIOS_DEBUG, "\t\tPersonality: 0x%x\n", ri->Personality); printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase); printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit); - printk(BIOS_DEBUG, "\t\tIoBase: 0x%x\n", ri->IoBase); - printk(BIOS_DEBUG, "\t\tIoLimit: 0x%x\n", ri->IoLimit); + printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", + ri->PciResourceIoBase); + printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", + ri->PciResourceIoLimit); printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase); printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit); printk(BIOS_DEBUG, "\t\tMmio32Base: 0x%x\n", ri->Mmio32Base); printk(BIOS_DEBUG, "\t\tMmio32Limit: 0x%x\n", ri->Mmio32Limit); printk(BIOS_DEBUG, "\t\tMmio64Base: 0x%llx\n", ri->Mmio64Base); printk(BIOS_DEBUG, "\t\tMmio64Limit: 0x%llx\n", ri->Mmio64Limit); - printk(BIOS_DEBUG, "\t\tPciResourceBusBase: 0x%x\n", - ri->PciResourceBusBase); - printk(BIOS_DEBUG, "\t\tPciResourceBusLimit: 0x%x\n", - ri->PciResourceBusLimit); - printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", - ri->PciResourceIoBase); - printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", - ri->PciResourceIoLimit); printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n", ri->PciResourceMem32Base); printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n", diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 3517522f62..02bab70e7c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -473,40 +473,46 @@ typedef struct { **/ UINT8 X2apic; -/** Offset 0x00BE - IIO ConfigIOU0 +/** Offset 0x00BE - Usage type for DDR frequency limit + Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +**/ + UINT8 DdrFreqLimit; + +/** Offset 0x00BF - Usage type for Memory Serial Debug Message Level + Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +**/ + UINT8 serialDebugMsgLvl; + +/** Offset 0x00C0 - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU0[8]; -/** Offset 0x00C6 - IIO ConfigIOU1 +/** Offset 0x00C8 - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU1[8]; -/** Offset 0x00CE - IIO ConfigIOU2 +/** Offset 0x00D0 - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU2[8]; -/** Offset 0x00D6 - IIO ConfigIOU3 +/** Offset 0x00D8 - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU3[8]; -/** Offset 0x00DE - IIO ConfigIOU4 +/** Offset 0x00E0 - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU4[8]; -/** Offset 0x00E6 -**/ - UINT8 UnusedUpdSpace2[2]; - /** Offset 0x00E8 - Usage type for IIO PCIE Config Table Ptr IIO PCIE Config Table Ptr **/ @@ -677,16 +683,17 @@ typedef struct { **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x0148 - SerialIoUartDebugEnable +/** Offset 0x0148 - PchDciEn + Enable or Disable Pch DciEn +**/ + UINT8 PchDciEn; + +/** Offset 0x0149 - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; -/** Offset 0x0149 -**/ - UINT8 UnusedUpdSpace3; - /** Offset 0x014A - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 @@ -716,7 +723,7 @@ typedef struct { /** Offset 0x015C **/ - UINT8 UnusedUpdSpace4[2]; + UINT8 UnusedUpdSpace2[2]; /** Offset 0x015E **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 8f9a91a0e9..79c41621c8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -188,18 +188,14 @@ typedef struct _STACK_RES { uint8_t Personality; // see STACK_TYPE for details uint8_t BusBase; uint8_t BusLimit; - uint16_t IoBase; // Base of IO configured for this stack - uint16_t IoLimit; // Limit of IO configured for this stack + uint16_t PciResourceIoBase; + uint16_t PciResourceIoLimit; uint32_t IoApicBase; // Base of IO configured for this stack uint32_t IoApicLimit; // Limit of IO configured for this stack uint32_t Mmio32Base; uint32_t Mmio32Limit; uint64_t Mmio64Base; uint64_t Mmio64Limit; - uint8_t PciResourceBusBase; // Base of Bus resource available for PCI devices - uint8_t PciResourceBusLimit; // Limit of Bus resource available for PCI devices - uint16_t PciResourceIoBase; // Base of IO resource available for PCI devices - uint16_t PciResourceIoLimit; // Limit of IO resource available for PCI devices uint32_t PciResourceMem32Base; uint32_t PciResourceMem32Limit; uint64_t PciResourceMem64Base; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 71ff6d5e8b..f85c4ff0ac 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -102,11 +102,11 @@ typedef struct SystemMemoryMapHob { UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved3[24518]; + UINT8 reserved3[24551]; UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS - UINT8 reserved4[8]; + UINT8 reserved4[24]; UINT32 MmiohBase; // MMIOH base in 64MB granularity |