diff options
| -rw-r--r-- | src/mainboard/google/corsola/romstage.c | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/rtc.h | 240 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/rtc.c | 361 |
4 files changed, 605 insertions, 0 deletions
diff --git a/src/mainboard/google/corsola/romstage.c b/src/mainboard/google/corsola/romstage.c index 07b9127719..d1e9e20639 100644 --- a/src/mainboard/google/corsola/romstage.c +++ b/src/mainboard/google/corsola/romstage.c @@ -2,8 +2,10 @@ #include <arch/stages.h> #include <soc/mt6366.h> +#include <soc/rtc.h> void platform_romstage_main(void) { mt6366_init(); + rtc_boot(); } diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 35f9873d26..b1624a3aef 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c wdt.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c +romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c ramstage-y += ../common/auxadc.c ramstage-y += emi.c @@ -54,6 +55,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c ramstage-y += ../common/wdt.c wdt.c ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c +ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8186/include/soc/rtc.h b/src/soc/mediatek/mt8186/include/soc/rtc.h new file mode 100644 index 0000000000..3a0c7cd100 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/rtc.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.13 + */ + +#ifndef SOC_MEDIATEK_MT8186_RTC_H +#define SOC_MEDIATEK_MT8186_RTC_H + +#include <soc/pmic_wrap_common.h> +#include <soc/rtc_common.h> +#include <stdbool.h> + +/* RTC registers */ +enum { + RTC_BBPU = 0x0588, + RTC_IRQ_STA = 0x058A, + RTC_IRQ_EN = 0x058C, + RTC_CII_EN = 0x058E, +}; + +enum { + RTC_TC_SEC = 0x0592, + RTC_TC_MIN = 0x0594, + RTC_TC_HOU = 0x0596, + RTC_TC_DOM = 0x0598, + RTC_TC_DOW = 0x059A, + RTC_TC_MTH = 0x059C, + RTC_TC_YEA = 0x059E, +}; + +enum { + RTC_AL_SEC = 0x05A0, + RTC_AL_MIN = 0x05A2, + RTC_AL_HOU = 0x05A4, + RTC_AL_DOM = 0x05A6, + RTC_AL_DOW = 0x05A8, + RTC_AL_MTH = 0x05AA, + RTC_AL_YEA = 0x05AC, + RTC_AL_MASK = 0x0590, +}; + +enum { + RTC_OSC32CON = 0x05AE, + RTC_CON = 0x05C4, + RTC_WRTGR = 0x05C2, +}; + +enum { + RTC_POWERKEY1 = 0x05B0, + RTC_POWERKEY2 = 0x05B2, +}; + +enum { + RTC_PDN1 = 0x05B4, + RTC_PDN2 = 0x05B6, + RTC_SPAR0 = 0x05B8, + RTC_SPAR1 = 0x05BA, + RTC_PROT = 0x05BC, + RTC_DIFF = 0x05BE, + RTC_CALI = 0x05C0, +}; + +enum { + RTC_BBPU_PWREN = 1U << 0, + RTC_BBPU_CLR = 1U << 1, + RTC_BBPU_INIT = 1U << 2, + RTC_BBPU_AUTO = 1U << 3, + RTC_BBPU_CLRPKY = 1U << 4, + RTC_BBPU_RELOAD = 1U << 5, + RTC_BBPU_CBUSY = 1U << 6, + + RTC_CBUSY_TIMEOUT_US = 8000, +}; + +enum { + RTC_CON_VBAT_LPSTA_RAW = 1U << 0, + RTC_CON_EOSC32_LPEN = 1U << 1, + RTC_CON_XOSC32_LPEN = 1U << 2, + RTC_CON_LPRST = 1U << 3, + RTC_CON_CDBO = 1U << 4, + RTC_CON_F32KOB = 1U << 5, + RTC_CON_GPO = 1U << 6, + RTC_CON_GOE = 1U << 7, + RTC_CON_GSR = 1U << 8, + RTC_CON_GSMT = 1U << 9, + RTC_CON_GPEN = 1U << 10, + RTC_CON_GPU = 1U << 11, + RTC_CON_GE4 = 1U << 12, + RTC_CON_GE8 = 1U << 13, + RTC_CON_GPI = 1U << 14, + RTC_CON_LPSTA_RAW = 1U << 15, +}; + +enum { + RTC_XOSCCALI_MASK = 0x1F << 0, + RTC_XOSC32_ENB = 1U << 5, + RTC_EMB_HW_MODE = 0U << 6, + RTC_EMB_K_EOSC32_MODE = 1U << 6, + RTC_EMB_SW_DCXO_MODE = 2U << 6, + RTC_EMB_SW_EOSC32_MODE = 3U << 6, + RTC_EMBCK_SEL_MODE_MASK = 3U << 6, + RTC_EMBCK_SRC_SEL = 1U << 8, + RTC_EMBCK_SEL_OPTION = 1U << 9, + RTC_GPS_CKOUT_EN = 1U << 10, + RTC_REG_XOSC32_ENB = 1U << 15, +}; + +enum { + RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13, + RTC_LPD_OPT_EOSC_LPD = 1U << 13, + RTC_LPD_OPT_XOSC_LPD = 2U << 13, + RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13, + RTC_LPD_OPT_MASK = 3U << 13, +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_SCK_TOP_CON0 = 0x050C, +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_TOP_CKPDN_CON0 = 0x010C, + PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E, + PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_RG_TOP_CKPDN_CON1 = 0x0112, + PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, + PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, + PMIC_RG_TOP_CKSEL_CON0 = 0x0118, + PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A, + PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C, +}; + +enum { + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10, + PMIC_RG_FQMTR_CK_PDN_SHIFT = 11, +}; + +/* PMIC DCXO Register Definition */ +enum { + PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW00_CLR = 0x078C, + PMIC_RG_DCXO_CW02 = 0x0790, + PMIC_RG_DCXO_CW07 = 0x079A, + PMIC_RG_DCXO_CW09 = 0x079E, + PMIC_RG_DCXO_CW11 = 0x07A2, + PMIC_RG_DCXO_CW13 = 0x07AA, + PMIC_RG_DCXO_CW15 = 0x07AE, + PMIC_RG_DCXO_CW16 = 0x07B0, + PMIC_RG_DCXO_CW21 = 0x07BA, + PMIC_RG_DCXO_CW23 = 0x07BE, + PMIC_RG_DCXO_ELR0 = 0x07C4, +}; + +enum { + PMIC_RG_TOP_TMA_KEY = 0x03A8, +}; + +/* PMIC Frequency Meter Definition */ +enum { + PMIC_RG_FQMTR_CKSEL = 0x0118, + PMIC_RG_FQMTR_RST = 0x013E, + PMIC_RG_FQMTR_CON0 = 0x0514, + PMIC_RG_FQMTR_WINSET = 0x0516, + PMIC_RG_FQMTR_DATA = 0x0518, + + FQMTR_TIMEOUT_US = 8000, +}; + +enum { + PMIC_FQMTR_FIX_CLK_26M = 0U << 0, + PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0, + PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0, + PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0, + PMIC_FQMTR_FIX_CLK_SMPS_CK = 4U << 0, + PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0, + PMIC_FQMTR_FIX_CLK_PMU_75K = 6U << 0, + PMIC_FQMTR_CKSEL_MASK = 7U << 0, +}; + +enum { + PMIC_FQMTR_RST_SHIFT = 8 +}; + +enum { + PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0, + PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0, + PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0, + PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0, + PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0, + PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0, + PMIC_FQMTR_CON0_TEST_CK = 6U << 0, + PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0, + PMIC_FQMTR_CON0_BUSY = 1U << 3, + PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4, + PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15, +}; + +enum { + RTC_FQMTR_LOW_BASE = 794 - 2, + RTC_FQMTR_HIGH_BASE = 794 + 2, +}; + +enum { + RTC_XOSCCALI_START = 0x00, + RTC_XOSCCALI_END = 0x1f, +}; + +/* external API */ +void rtc_bbpu_power_on(void); +int rtc_init(int recover); +bool rtc_gpio_init(void); +void rtc_boot(void); +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size); + +static inline s32 rtc_read(u16 addr, u16 *rdata) +{ + s32 ret; + + ret = pwrap_read(addr, rdata); + if (ret) + rtc_info("pwrap_read failed: ret=%d\n", ret); + + return ret; +} + +static inline s32 rtc_write(u16 addr, u16 wdata) +{ + s32 ret; + + ret = pwrap_write(addr, wdata); + if (ret) + rtc_info("pwrap_write failed: ret=%d\n", ret); + + return ret; +} + +#endif /* SOC_MEDIATEK_MT8186_RTC_H */ diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c new file mode 100644 index 0000000000..346fca64b9 --- /dev/null +++ b/src/soc/mediatek/mt8186/rtc.c @@ -0,0 +1,361 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.13 + */ + +#include <delay.h> +#include <halt.h> +#include <soc/rtc.h> +#include <soc/rtc_common.h> +#include <soc/mt6366.h> +#include <soc/pmic_wrap.h> +#include <timer.h> + +#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) + +/* Initialize RTC setting of using DCXO clock */ +static bool rtc_enable_dcxo(void) +{ + u16 bbpu, con, osc32con, sec; + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + mdelay(1); + if (!rtc_writeif_unlock()) { + rtc_info("rtc_writeif_unlock() failed\n"); + return false; + } + + rtc_read(RTC_OSC32CON, &osc32con); + osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK + | RTC_GPS_CKOUT_EN); + osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB + | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION; + if (!rtc_xosc_write(osc32con)) { + rtc_info("rtc_xosc_write() failed\n"); + return false; + } + + rtc_read(RTC_CON, &con); + rtc_read(RTC_OSC32CON, &osc32con); + rtc_read(RTC_AL_SEC, &sec); + rtc_info("con = %#x, osc32con = %#x, sec = %#x\n", con, osc32con, sec); + + return true; +} + +/* Initialize RTC related gpio */ +bool rtc_gpio_init(void) +{ + u16 con; + + /* RTC_32K1V8 clock change from 128k div 4 source to RTC 32k source */ + pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3); + + /* Export 32K clock RTC_32K1V8_1 */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1); + + /* Export 32K clock RTC_32K2V8 */ + rtc_read(RTC_CON, &con); + con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN + | RTC_CON_XOSC32_LPEN); + con |= (RTC_CON_GPEN | RTC_CON_GOE); + con &= ~RTC_CON_F32KOB; + rtc_write(RTC_CON, con); + + return rtc_write_trigger(); +} + +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) +{ + u16 bbpu, osc32con; + u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; + struct stopwatch sw; + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + rtc_read(RTC_OSC32CON, &osc32con); + if (rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) | + (val & RTC_XOSCCALI_MASK))) { + rtc_info("rtc_xosc_write() failed\n"); + return false; + } + + /* Enable FQMTR clock */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_CK_PDN_SHIFT); + + /* FQMTR reset */ + pwrap_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT); + do { + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); + } while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY)); + rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst); + /* FQMTR normal */ + pwrap_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT); + + /* Set frequency meter window value (0=1X32K(fixed clock)) */ + rtc_write(PMIC_RG_FQMTR_WINSET, window_size); + /* Enable 26M and set test clock source */ + rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src); + /* Enable 26M -> delay 100us -> enable FQMTR */ + udelay(100); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* Enable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN); + udelay(100); + + stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US); + /* FQMTR read until ready */ + if (!wait_us(FQMTR_TIMEOUT_US, + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy) == 0 && + !(fqmtr_busy & PMIC_FQMTR_CON0_BUSY))) { + rtc_info("get frequency time out: %#x\n", fqmtr_busy); + return false; + } + + /* Read data should be closed to 26M/32k = 794 */ + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* Disable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN); + /* Disable FQMTR -> delay 100us -> disable 26M */ + udelay(100); + /* Disable 26M */ + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + rtc_write(PMIC_RG_FQMTR_CON0, + fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN); + rtc_info("input = %#x, output = %#x\n", val, fqmtr_data); + + /* Disable FQMTR clock */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_CK_PDN_SHIFT); + + return fqmtr_data; +} + +/* Low power detect setting */ +static bool rtc_lpd_init(void) +{ + u16 con, sec; + + /* Set RTC_LPD_OPT */ + rtc_read(RTC_AL_SEC, &sec); + sec |= RTC_LPD_OPT_F32K_CK_ALIVE; + rtc_write(RTC_AL_SEC, sec); + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + /* Initialize XOSC32 to detect 32k clock stop */ + rtc_read(RTC_CON, &con); + con |= RTC_CON_XOSC32_LPEN; + if (!rtc_lpen(con)) + return false; + + /* Initialize EOSC32 to detect RTC low power */ + rtc_read(RTC_CON, &con); + con |= RTC_CON_EOSC32_LPEN; + if (!rtc_lpen(con)) + return false; + + rtc_read(RTC_CON, &con); + con &= ~RTC_CON_XOSC32_LPEN; + rtc_write(RTC_CON, con); + + /* Set RTC_LPD_OPT */ + rtc_read(RTC_AL_SEC, &sec); + sec &= ~RTC_LPD_OPT_MASK; + sec |= RTC_LPD_OPT_EOSC_LPD; + rtc_write(RTC_AL_SEC, sec); + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + return true; +} + +static bool rtc_hw_init(void) +{ + u16 bbpu; + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT); + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + udelay(500); + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + rtc_read(RTC_BBPU, &bbpu); + if (bbpu & RTC_BBPU_INIT) { + rtc_info("timeout\n"); + return false; + } + + return true; +} + +static void mt6366_dcxo_disable_unused(void) +{ + /* Disable clock buffer XO_CEL */ + rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800); + /* Mask bblpm request and switch off bblpm mode */ + rtc_write(PMIC_RG_DCXO_CW23, 0x0052); +} + +/* Check RTC Initialization */ +int rtc_init(int recover) +{ + int ret; + + rtc_info("recovery: %d\n", recover); + + /* Write powerkeys to enable RTC functions */ + if (!rtc_powerkey_init()) { + ret = -RTC_STATUS_POWERKEY_INIT_FAIL; + goto err; + } + + /* Write interface unlock need to be set after powerkey match */ + if (!rtc_writeif_unlock()) { + ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL; + goto err; + } + + rtc_osc_init(); + + /* In recovery mode, we need 20ms delay for register setting. */ + if (recover) + mdelay(20); + + if (!rtc_gpio_init()) { + ret = -RTC_STATUS_GPIO_INIT_FAIL; + goto err; + } + + if (!rtc_hw_init()) { + ret = -RTC_STATUS_HW_INIT_FAIL; + goto err; + } + + if (!rtc_reg_init()) { + ret = -RTC_STATUS_REG_INIT_FAIL; + goto err; + } + + if (!rtc_lpd_init()) { + ret = -RTC_STATUS_LPD_INIT_FAIL; + goto err; + } + + /* + * After lpd init, powerkeys need to be written again to enable + * low power detect function. + */ + if (!rtc_powerkey_init()) { + ret = -RTC_STATUS_POWERKEY_INIT_FAIL; + goto err; + } + + return RTC_STATUS_OK; +err: + rtc_info("init failed: ret = %d\n", ret); + return ret; +} + +/* Enable RTC bbpu */ +void rtc_bbpu_power_on(void) +{ + u16 bbpu; + int ret; + + /* Pull powerhold high, control by pmic */ + mt6366_set_power_hold(true); + + /* Pull PWRBB high */ + bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN; + rtc_write(RTC_BBPU, bbpu); + ret = rtc_write_trigger(); + rtc_info("rtc_write_trigger = %d\n", ret); + + rtc_read(RTC_BBPU, &bbpu); + rtc_info("done BBPU = %#x\n", bbpu); +} + +static void dcxo_init(void) +{ + /* Buffer setting */ + rtc_write(PMIC_RG_DCXO_CW15, 0xA2AA); + rtc_write(PMIC_RG_DCXO_CW13, 0x98E9); + rtc_write(PMIC_RG_DCXO_CW16, 0x9855); + + /* 26M enable control */ + /* Enable clock buffer XO_SOC, XO_CEL */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4805); + rtc_write(PMIC_RG_DCXO_CW11, 0x8000); + + /* Load thermal coefficient */ + rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); + rtc_write(PMIC_RG_DCXO_CW21, 0x12A7); + rtc_write(PMIC_RG_DCXO_ELR0, 0xD004); + rtc_write(PMIC_RG_TOP_TMA_KEY, 0x0000); + + /* Adjust OSC FPM setting */ + rtc_write(PMIC_RG_DCXO_CW07, 0x8FFE); + + /* Re-calibrate OSC current */ + rtc_write(PMIC_RG_DCXO_CW09, 0x008F); + udelay(100); + rtc_write(PMIC_RG_DCXO_CW09, 0x408F); + mdelay(5); + + mt6366_dcxo_disable_unused(); +} + +/* Initialize rtc boot flow */ +void rtc_boot(void) +{ + /* DCXO clock initialized settings */ + dcxo_init(); + + /* DCXO 32k initialized settings */ + pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); + pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); + + /* Use DCXO 32K clock */ + if (!rtc_enable_dcxo()) + rtc_info("rtc_enable_dcxo() failed\n"); + + rtc_boot_common(); + rtc_bbpu_power_on(); +} |