diff options
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 11 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 15 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/Kconfig | 8 |
4 files changed, 16 insertions, 26 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 2ad32097de..bbf0710b7f 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -522,4 +522,15 @@ config FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable to return any ERROR status. +config FSP_PUBLISH_MBP_HOB + bool + default n if CHROMEOS + default y + help + This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. + Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. + + ChromeOS devices typically do not require the MBP information, hence it is disabled + by default on ChromeOS. + endif diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index f7c585a0bd..c1cc993efb 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -511,18 +511,13 @@ config INTEL_GMA_BCLM_OFFSET config INTEL_GMA_BCLM_WIDTH default 32 +# Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on +# MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't +# occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the +# later platforms so creation of MBP HOB can be skipped for ADL-N based platforms. config FSP_PUBLISH_MBP_HOB bool - default n if CHROMEOS && (SOC_INTEL_ALDERLAKE_PCH_N) - default y - help - This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. - Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. - - Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on - MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't - occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the - later platforms so creation of MBP HOB can be skipped for ADL-N based platforms. + default y if !SOC_INTEL_ALDERLAKE_PCH_N config INCLUDE_HSPHY_IN_FMAP bool "Include PCIe 5.0 HSPHY firmware in flash" diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 79ef3e8c75..753af7cb67 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -380,14 +380,6 @@ config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET hex default 0x800000 -config FSP_PUBLISH_MBP_HOB - bool - default n if CHROMEOS - default y - help - This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. - Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. - config BUILDING_WITH_DEBUG_FSP bool "Debug FSP is used for the build" default n diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 9a5fc61fb1..e5f7c9201e 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -248,12 +248,4 @@ config BUILDING_WITH_DEBUG_FSP help Set this option if debug build of FSP is used. -config FSP_PUBLISH_MBP_HOB - bool - default n if CHROMEOS - default y - help - This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. - Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. - endif |