diff options
29 files changed, 1445 insertions, 0 deletions
diff --git a/src/mainboard/system76/kbl-u/Kconfig b/src/mainboard/system76/kbl-u/Kconfig new file mode 100644 index 0000000000..e4421d179a --- /dev/null +++ b/src/mainboard/system76/kbl-u/Kconfig @@ -0,0 +1,60 @@ +if BOARD_SYSTEM76_GALP3_B + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIEXP_HOTPLUG + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + default "system76/kbl-u" + +config VARIANT_DIR + default "galp3-b" if BOARD_SYSTEM76_GALP3_B + +config MAINBOARD_PART_NUMBER + default "galp3-b" if BOARD_SYSTEM76_GALP3_B + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Galago Pro" + +config MAINBOARD_VERSION + default "galp3-b" if BOARD_SYSTEM76_GALP3_B + +config CBFS_SIZE + default 0x600000 + +config CONSOLE_POST + default y + +config ONBOARD_VGA_IS_PRIMARY + default y + +config UART_FOR_CONSOLE + default 2 + +config DIMM_MAX + default 2 + +config DIMM_SPD_SIZE + default 512 + +config VGA_BIOS_ID + default "8086,5917" if BOARD_SYSTEM76_GALP3_B + +config POST_DEVICE + default n + +endif diff --git a/src/mainboard/system76/kbl-u/Kconfig.name b/src/mainboard/system76/kbl-u/Kconfig.name new file mode 100644 index 0000000000..8af68d8805 --- /dev/null +++ b/src/mainboard/system76/kbl-u/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SYSTEM76_GALP3_B + bool "galp3-b" diff --git a/src/mainboard/system76/kbl-u/Makefile.inc b/src/mainboard/system76/kbl-u/Makefile.inc new file mode 100644 index 0000000000..d749e412cc --- /dev/null +++ b/src/mainboard/system76/kbl-u/Makefile.inc @@ -0,0 +1,8 @@ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +ramstage-y += ramstage.c +ramstage-y += gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/kbl-u/acpi/ac.asl b/src/mainboard/system76/kbl-u/acpi/ac.asl new file mode 100644 index 0000000000..7326676198 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/ac.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (AC) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + Return (ACFG) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/battery.asl b/src/mainboard/system76/kbl-u/acpi/battery.asl new file mode 100644 index 0000000000..f3a8a9adb7 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/battery.asl @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (BFCC, Zero) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package (0x0D) + { + One, // 0 - Power Unit + 0xFFFFFFFF, // 1 - Design Capacity + 0xFFFFFFFF, // 2 - Last Full Charge Capacity + One, // 3 - Battery Technology + 0x39D0, // 4 - Design Voltage + Zero, // 5 - Design Capacity of Warning + Zero, // 6 - Design Capacity of Low + 0x40, // 7 - Battery Capacity Granularity 1 + 0x40, // 8 - Battery Capacity Granularity 2 + "BAT", // 9 - Model Number + "0001", // 10 - Serial Number + "LION", // 11 - Battery Type + "Notebook" // 12 - OEM Information + }) + Method (IVBI, 0, NotSerialized) + { + PBIF [1] = 0xFFFFFFFF + PBIF [2] = 0xFFFFFFFF + PBIF [4] = 0xFFFFFFFF + PBIF [9] = " " + PBIF [10] = " " + PBIF [11] = " " + PBIF [12] = " " + BFCC = Zero + } + + Method (UPBI, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF) + PBIF [1] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF) + PBIF [2] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF) + PBIF [4] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF) + PBIF [5] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF) + PBIF [6] = Local0 + PBIF [9] = "BAT" + PBIF [10] = "0001" + PBIF [11] = "LION" + PBIF [12] = "Notebook" + } + Else + { + IVBI () + } + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBI () + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Name (PBST, Package (0x04) + { + Zero, // 0 - Battery state + 0xFFFFFFFF, // 1 - Battery present rate + 0xFFFFFFFF, // 2 - Battery remaining capacity + 0x3D90 // 3 - Battery present voltage + }) + Method (IVBS, 0, NotSerialized) + { + PBST [0] = Zero + PBST [1] = 0xFFFFFFFF + PBST [2] = 0xFFFFFFFF + PBST [3] = 0x2710 + } + + Method (UPBS, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = Zero + Local1 = Zero + If (^^AC.ACFG) + { + If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02)) + { + Local0 |= 0x02 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + } + Else + { + Local0 |= One + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + + Local7 = (Local1 & 0x8000) + If ((Local7 == 0x8000)) + { + Local1 ^= 0xFFFF + } + + Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF) + Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF) + PBST [0] = Local0 + PBST [1] = Local1 + PBST [2] = Local2 + PBST [3] = Local3 + If ((BFCC != ^^PCI0.LPCB.EC0.BFC0)) + { + Notify (BAT0, 0x81) // Information Change + } + } + Else + { + IVBS () + } + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBS () + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/buttons.asl b/src/mainboard/system76/kbl-u/acpi/buttons.asl new file mode 100644 index 0000000000..103c794595 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/buttons.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 }) +} + +Device (SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 }) +} diff --git a/src/mainboard/system76/kbl-u/acpi/ec.asl b/src/mainboard/system76/kbl-u/acpi/ec.asl new file mode 100644 index 0000000000..de25eca129 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/ec.asl @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_GPE, 0x50 /* GPP_E16 */) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + + #include "acpi/ec_ram.asl" + + Name (ECOK, Zero) + Method (_REG, 2, Serialized) // _REG: Region Availability + { + Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1)))) + If ((Arg0 == 0x03) && (Arg1 == One)) { + // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys + ECOS = 1 + + // Enable software display brightness keys + WINF = 1 + + // Set current AC state + ^^^^AC.ACFG = ADP + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + + // Notify of changes + Notify(^^^^AC, Zero) + Notify(^^^^BAT0, Zero) + + PNOT () + + // EC is now available + ECOK = Arg1 + + // Reset System76 Device + ^^^^S76D.RSET() + } + } + + Name (S3OS, Zero) + Method (PTS, 1, Serialized) { + Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) + If (ECOK) { + // Save ECOS during sleep + S3OS = ECOS + + // Clear wake cause + WFNO = Zero + } + } + + Method (WAK, 1, Serialized) { + Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) + If (ECOK) { + // Restore ECOS after sleep + ECOS = S3OS + + // Set current AC state + ^^^^AC.ACFG = ADP + + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + + // Notify of changes + Notify(^^^^AC, Zero) + Notify(^^^^BAT0, Zero) + + // Reset System76 Device + ^^^^S76D.RSET() + } + } + + Method (_Q0A, 0, NotSerialized) // Touchpad Toggle + { + Debug = "EC: Touchpad Toggle" + } + + Method (_Q0B, 0, NotSerialized) // Screen Toggle + { + Debug = "EC: Screen Toggle" + } + + Method (_Q0C, 0, NotSerialized) // Mute + { + Debug = "EC: Mute" + } + + Method (_Q0D, 0, NotSerialized) // Keyboard Backlight + { + Debug = "EC: Keyboard Backlight" + } + + Method (_Q0E, 0, NotSerialized) // Volume Down + { + Debug = "EC: Volume Down" + } + + Method (_Q0F, 0, NotSerialized) // Volume Up + { + Debug = "EC: Volume Up" + } + + Method (_Q10, 0, NotSerialized) // Switch Video Mode + { + Debug = "EC: Switch Video Mode" + } + + Method (_Q11, 0, NotSerialized) // Brightness Down + { + Debug = "EC: Brightness Down" + if (^^^^HIDD.HRDY) { + ^^^^HIDD.HPEM (20) + } + } + + Method (_Q12, 0, NotSerialized) // Brightness Up + { + Debug = "EC: Brightness Up" + if (^^^^HIDD.HRDY) { + ^^^^HIDD.HPEM (19) + } + } + + Method (_Q13, 0, NotSerialized) // Camera Toggle + { + Debug = "EC: Camera Toggle" + } + + Method (_Q14, 0, NotSerialized) // Airplane Mode + { + Debug = "EC: Airplane Mode" + if (^^^^HIDD.HRDY) { + ^^^^HIDD.HPEM (8) + } + // TODO: hardware airplane mode + } + + Method (_Q15, 0, NotSerialized) // Suspend Button + { + Debug = "EC: Suspend Button" + Notify (SLPB, 0x80) + } + + Method (_Q16, 0, NotSerialized) // AC Detect + { + Debug = "EC: AC Detect" + ^^^^AC.ACFG = ADP + Notify (AC, 0x80) // Status Change + If (BAT0) + { + Notify (^^^^BAT0, 0x81) // Information Change + Notify (^^^^BAT0, 0x80) // Status Change + } + } + + Method (_Q17, 0, NotSerialized) // BAT0 Update + { + Debug = "EC: BAT0 Update (17)" + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q19, 0, NotSerialized) // BAT0 Update + { + Debug = "EC: BAT0 Update (19)" + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q1B, 0, NotSerialized) // Lid Close + { + Debug = "EC: Lid Close" + Notify (LID0, 0x80) + } + + Method (_Q1C, 0, NotSerialized) // Thermal Trip + { + Debug = "EC: Thermal Trip" + /* TODO + Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change + Notify (\_TZ.TZ0, 0x80) // Thermal Status Change + */ + } + + Method (_Q1D, 0, NotSerialized) // Power Button + { + Debug = "EC: Power Button" + Notify (PWRB, 0x80) + } + + Method (_Q50, 0, NotSerialized) // Other Events + { + Local0 = OEM4 + If (Local0 == 0x8A) { + Debug = "EC: White Keyboard Backlight" + Notify (^^^^S76D, 0x80) + } ElseIf (Local0 == 0x9F) { + Debug = "EC: Color Keyboard Toggle" + Notify (^^^^S76D, 0x81) + } ElseIf (Local0 == 0x81) { + Debug = "EC: Color Keyboard Down" + Notify (^^^^S76D, 0x82) + } ElseIf (Local0 == 0x82) { + Debug = "EC: Color Keyboard Up" + Notify (^^^^S76D, 0x83) + } ElseIf (Local0 == 0x80) { + Debug = "EC: Color Keyboard Color Change" + Notify (^^^^S76D, 0x84) + } Else { + Debug = Concatenate("EC: Other: ", ToHexString(Local0)) + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/ec_ram.asl b/src/mainboard/system76/kbl-u/acpi/ec_ram.asl new file mode 100644 index 0000000000..0b6d27e051 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/ec_ram.asl @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) +Field (ERAM, ByteAcc, Lock, Preserve) +{ + NMSG, 8, + SLED, 4, + Offset (0x02), + MODE, 1, + FAN0, 1, + TME0, 1, + TME1, 1, + FAN1, 1, + , 2, + Offset (0x03), + LSTE, 1, // Lid is open + LSW0, 1, + LWKE, 1, // Lid wake + WAKF, 1, + , 2, + PWKE, 1, + MWKE, 1, + AC0, 8, + PSV, 8, + CRT, 8, + TMP, 8, + AC1, 8, + BBST, 8, + Offset (0x0B), + Offset (0x0C), + Offset (0x0D), + Offset (0x0E), + SLPT, 8, + SWEJ, 1, + SWCH, 1, + Offset (0x10), + ADP, 1, // AC adapter connected + AFLT, 1, + BAT0, 1, + BAT1, 1, + , 3, + PWOF, 1, + WFNO, 8, // Wake cause + BPU0, 32, + BDC0, 32, // Battery design capacity + BFC0, 32, // Battery full capacity + BTC0, 32, + BDV0, 32, // Battery design voltage + BST0, 32, // Battery status + BPR0, 32, // Battery current + BRC0, 32, // Battery remaining capacity + BPV0, 32, // Battery voltage + BTP0, 16, + BRS0, 16, + BCW0, 32, + BCL0, 32, + BCG0, 32, + BG20, 32, + BMO0, 64, + BIF0, 64, + BSN0, 32, + BTY0, 64, + Offset (0x68), + ECOS, 8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver + LNXD, 8, + ECPS, 8, + Offset (0x6C), + BTMP, 16, + EVTN, 8, + Offset (0x72), + PRCL, 8, + PRC0, 8, + PRC1, 8, + PRCM, 8, + PRIN, 8, + PSTE, 8, + PCAD, 8, + PEWL, 8, + PWRL, 8, + PECD, 8, + PEHI, 8, + PECI, 8, + PEPL, 8, + PEPM, 8, + PWFC, 8, + PECC, 8, + PDT0, 8, + PDT1, 8, + PDT2, 8, + PDT3, 8, + PRFC, 8, + PRS0, 8, + PRS1, 8, + PRS2, 8, + PRS3, 8, + PRS4, 8, + PRCS, 8, + PEC0, 8, + PEC1, 8, + PEC2, 8, + PEC3, 8, + CMDR, 8, + CVRT, 8, + GTVR, 8, + FANT, 8, + SKNT, 8, + AMBT, 8, + MCRT, 8, + DIM0, 8, + DIM1, 8, + PMAX, 8, + PPDT, 8, + PECH, 8, + PMDT, 8, + TSD0, 8, + TSD1, 8, + TSD2, 8, + TSD3, 8, + CPUP, 16, + MCHP, 16, + SYSP, 16, + CPAP, 16, + MCAP, 16, + SYAP, 16, + CFSP, 16, + CPUE, 16, + Offset (0xC6), + Offset (0xC7), + VGAT, 8, + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, // Extra SCI data + Offset (0xCE), + DUT1, 8, // Fan 1 duty + DUT2, 8, // Fan 2 duty + RPM1, 16, // Fan 1 RPM + RPM2, 16, // Fan 2 RPM + RPM4, 16, + Offset (0xD7), + DTHL, 8, + DTBP, 8, + AIRP, 8, // Airplane mode LED + WINF, 8, // Enable ACPI brightness controls + RINF, 8, + Offset (0xDD), + INF2, 8, + MUTE, 1, + Offset (0xE0), + RPM3, 16, + ECKS, 8, + Offset (0xE4), + , 4, + XTUF, 1, + EP12, 1, + Offset (0xE5), + INF3, 8, + Offset (0xE7), + GFOF, 8, + Offset (0xF0), + PL1T, 16, + PL2T, 16, + TAUT, 8, + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8, +} diff --git a/src/mainboard/system76/kbl-u/acpi/gpe.asl b/src/mainboard/system76/kbl-u/acpi/gpe.asl new file mode 100644 index 0000000000..b60a132f9c --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/gpe.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// GPP_C19 SCI +Method (_L13, 0, Serialized) { + Debug = Concatenate("GPE _L13: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == 1) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/hid.asl b/src/mainboard/system76/kbl-u/acpi/hid.asl new file mode 100644 index 0000000000..6610c2e1bc --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/hid.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (HIDD) +{ + Name (_HID, "INT33D5") + Name (HBSY, Zero) + Name (HIDX, Zero) + Name (HRDY, Zero) + + Method (HDEM, 0, Serialized) + { + HBSY = Zero + Return (HIDX) + } + + Method (HDMM, 0, Serialized) + { + Return (Zero) + } + + Method (HDSM, 1, Serialized) + { + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + HBSY = One + HIDX = Arg0 + + Notify (HIDD, 0xC0) + Local0 = Zero + While ((Local0 < 0xFA) && HBSY) + { + Sleep (0x04) + Local0++ + } + + If (HBSY == One) + { + HBSY = Zero + HIDX = Zero + Return (One) + } + Else + { + Return (Zero) + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/lid.asl b/src/mainboard/system76/kbl-u/acpi/lid.asl new file mode 100644 index 0000000000..582c38d87c --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/lid.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 }) + + Method (_LID, 0, NotSerialized) { + DEBUG = "LID: _LID" + If (^^PCI0.LPCB.EC0.ECOK) { + Return (^^PCI0.LPCB.EC0.LSTE) + } Else { + Return (One) + } + } + + Method (_PSW, 1, NotSerialized) { + DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0)) + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.LWKE = Arg0 + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/mainboard.asl b/src/mainboard/system76/kbl-u/acpi/mainboard.asl new file mode 100644 index 0000000000..11735e8e01 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "ac.asl" + #include "battery.asl" + #include "buttons.asl" + #include "hid.asl" + #include "lid.asl" + #include "s76.asl" + #include "sleep.asl" +} + +Scope (_GPE) { + #include "gpe.asl" +} diff --git a/src/mainboard/system76/kbl-u/acpi/s76.asl b/src/mainboard/system76/kbl-u/acpi/s76.asl new file mode 100644 index 0000000000..399e569734 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/s76.asl @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Notifications: +// 0x80 - hardware backlight toggle +// 0x81 - backlight toggle +// 0x82 - backlight down +// 0x83 - backlight up +// 0x84 - backlight color change +Device (S76D) { + Name (_HID, "17761776") + Name (_UID, 0) + + Method (RSET, 0, Serialized) { + Debug = "S76D: RSET" + SAPL(0) + SKBL(0) + } + + Method (INIT, 0, Serialized) { + Debug = "S76D: INIT" + RSET() + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use software control + ^^PCI0.LPCB.EC0.ECOS = 2 + Return (0) + } Else { + Return (1) + } + } + + Method (FINI, 0, Serialized) { + Debug = "S76D: FINI" + RSET() + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use hardware control + ^^PCI0.LPCB.EC0.ECOS = 1 + Return (0) + } Else { + Return (1) + } + } + + // Get Airplane LED + Method (GAPL, 0, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (^^PCI0.LPCB.EC0.AIRP & 0x40) { + Return (1) + } + } + Return (0) + } + + // Set Airplane LED + Method (SAPL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0) { + ^^PCI0.LPCB.EC0.AIRP |= 0x40 + } Else { + ^^PCI0.LPCB.EC0.AIRP &= 0xBF + } + } + } + + // Get KB LED + Method (GKBL, 0, Serialized) { + Local0 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = One + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Local0 = ^^PCI0.LPCB.EC0.FBUF + ^^PCI0.LPCB.EC0.FCMD = Zero + } + Return (Local0) + } + + // Set KB Led + Method (SKBL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = Zero + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/sleep.asl b/src/mainboard/system76/kbl-u/acpi/sleep.asl new file mode 100644 index 0000000000..48c50e075e --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.PCI0.LPCB.EC0.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/system76/kbl-u/acpi/superio.asl b/src/mainboard/system76/kbl-u/acpi/superio.asl new file mode 100644 index 0000000000..55b1db5b11 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/system76/kbl-u/board_info.txt b/src/mainboard/system76/kbl-u/board_info.txt new file mode 100644 index 0000000000..56e98a39e3 --- /dev/null +++ b/src/mainboard/system76/kbl-u/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: kbl-u +Category: laptop +Release year: 2018 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/kbl-u/bootblock.c b/src/mainboard/system76/kbl-u/bootblock.c new file mode 100644 index 0000000000..8d06adc9d7 --- /dev/null +++ b/src/mainboard/system76/kbl-u/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <mainboard/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/system76/kbl-u/cmos.default b/src/mainboard/system76/kbl-u/cmos.default new file mode 100644 index 0000000000..06b04332a2 --- /dev/null +++ b/src/mainboard/system76/kbl-u/cmos.default @@ -0,0 +1,2 @@ +boot_option=Fallback +debug_level=Debug diff --git a/src/mainboard/system76/kbl-u/cmos.layout b/src/mainboard/system76/kbl-u/cmos.layout new file mode 100644 index 0000000000..ac817525dd --- /dev/null +++ b/src/mainboard/system76/kbl-u/cmos.layout @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +984 16 h 0 check_sum + +enumerations + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 983 984 diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb new file mode 100644 index 0000000000..6322394ac1 --- /dev/null +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -0,0 +1,191 @@ +chip soc/intel/skylake + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART + }" + + # Serial IRQ + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Power + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + # FSP Configuration + register "SkipExtGfxScan" = "1" + register "SaGv" = "SaGv_Enabled" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 5A | 64A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(5), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(64), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device ref system_agent on end + device ref igpu on end + device ref sa_thermal on end + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left + end + device ref thermal on end + device ref sata on + register "SataSalpSupport" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataSpeedLimit" = "2" + end + device ref pcie_rp1 on + # Root port #1 x4 (TBT) + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "4" + register "PcieRpClkSrcNumber[0]" = "4" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" + end + device ref pcie_rp5 on + # Root port #5 x1 (LAN) + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + end + device ref pcie_rp6 on + # Root port #6 x1 (WLAN) + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "2" + register "PcieRpClkSrcNumber[5]" = "2" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + end + device ref pcie_rp9 on + # Root port #9 x4 (NVMe) + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end + device ref lpc_espi on + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x00040069" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb off end + device ref pmc on + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + end + device ref hda on end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/system76/kbl-u/dsdt.asl b/src/mainboard/system76/kbl-u/dsdt.asl new file mode 100644 index 0000000000..f93c3f68a8 --- /dev/null +++ b/src/mainboard/system76/kbl-u/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/kbl-u/gpio.c b/src/mainboard/system76/kbl-u/gpio.c new file mode 100644 index 0000000000..5c5662e1fc --- /dev/null +++ b/src/mainboard/system76/kbl-u/gpio.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_NC(GPD0, NONE), // PM_BATLOW# + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), // AC_PRESENT + _PAD_CFG_STRUCT(GPD2, 0x880500, 0x0), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUSCLK + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // PCH_SLP_WLAN# + PAD_NC(GPD10, NONE), // SLP_S5# + PAD_NC(GPD11, NONE), // PCH_GPD11 + + /* ------- GPIO Group A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0 + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1 + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2 + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3 + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ + PAD_NC(GPP_A7, NONE), // G_INT1 + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // PCLK_TPM + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), // LAN_WAKEUP# + PAD_NC(GPP_A12, NONE), // PCH_GPP_A12 + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE# + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), // SUSACK# + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_GPO(GPP_A18, 1, DEEP), // TBTA_ACE_GPIO3 + PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN + PAD_CFG_GPO(GPP_A20, 0, DEEP), // TBTA_ACE_GPIO0 + PAD_CFG_GPO(GPP_A21, 1, PLTRST), // TBT_FRC_PWR + PAD_CFG_GPO(GPP_A22, 0, PWROK), // PS8338B_SW + PAD_CFG_GPO(GPP_A23, 0, PWROK), // PS8338B_PCH + + /* ------- GPIO Group B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // CORE_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // CORE_VID1 + PAD_NC(GPP_B2, NONE), // VRALERT# + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), // PCIECLKRQ0# + PAD_NC(GPP_B6, NONE), // PCIECLKRQ1# + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ# + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ# + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR + PAD_NC(GPP_B15, NONE), // PCH_GPP_B15 + PAD_NC(GPP_B16, NONE), // PCH_GPP_B16 + PAD_NC(GPP_B17, NONE), // PCH_GPP_B17 + PAD_NC(GPP_B18, NONE), // GSPI0_BBS0 - No Reboot strap + PAD_NC(GPP_B19, NONE), // PCH_GPP_B19 + PAD_NC(GPP_B20, NONE), // PCH_GPP_B20 + PAD_NC(GPP_B21, NONE), // PCH_GPP_B21 + PAD_NC(GPP_B22, NONE), // PCH_GPP_B22 - Boot BIOS strap + PAD_NC(GPP_B23, NONE), // PCH_GPP_B23 + + /* ------- GPIO Group C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 + PAD_NC(GPP_C3, NONE), // SML0CLK + PAD_NC(GPP_C4, NONE), // SML0DATA + PAD_NC(GPP_C5, NONE), // PCH_GPP_C5 + PAD_NC(GPP_C6, NONE), // SML1CLK + PAD_NC(GPP_C7, NONE), // SML1DATA + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), // TBTA_ACE_GPIO2 + _PAD_CFG_STRUCT(GPP_C13, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT + PAD_NC(GPP_C14, NONE), // TBTA_MRESET + PAD_NC(GPP_C15, NONE), // TBTA_ACE_GPIO7 + PAD_NC(GPP_C16, NONE), // T_SDA + PAD_NC(GPP_C17, NONE), // T_SCL + PAD_NC(GPP_C18, NONE), + _PAD_CFG_STRUCT(GPP_C19, 0x40880100, 0x0000), // SWI# + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_NC(GPP_C22, NONE), // UEART2_RTS_N + PAD_NC(GPP_C23, NONE), // UART2_CTS_N + + /* ------- GPIO Group D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), // PCH_GPP_D4 + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON + PAD_NC(GPP_D9, NONE), // T_INT + PAD_NC(GPP_D10, NONE), // EDP_DET + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPI(GPP_D21, NONE, DEEP), // TPM_DET# + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group E ------- */ + PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 + PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT# + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), // SATAGP2 + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), // DEVSLP0 + PAD_NC(GPP_E5, NONE), // DEVSLP1 + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2 + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATA_LED# + PAD_NC(GPP_E9, NONE), // USB_OC#12 + PAD_NC(GPP_E10, NONE), // USB_OC#34 + PAD_NC(GPP_E11, NONE), // USB_OC#56 + PAD_NC(GPP_E12, NONE), // USB_OC#78 + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI# + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), // SCI# + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), // MDP_CTRLDATA + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), // HDMI_CTRLDATA + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group F ------- */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), // LIGHT_KB_DET# + + /* ------- GPIO Group G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_CFG_GPI(GPP_G1, NONE, DEEP), // TBT Detect + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), // ASM1543_I_SEL0 + PAD_NC(GPP_G4, NONE), // ASM1543_I_SEL1 + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/kbl-u/gpio_early.c b/src/mainboard/system76/kbl-u/gpio_early.c new file mode 100644 index 0000000000..80f37c6553 --- /dev/null +++ b/src/mainboard/system76/kbl-u/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/kbl-u/include/mainboard/gpio.h b/src/mainboard/system76/kbl-u/include/mainboard/gpio.h new file mode 100644 index 0000000000..c6393beebb --- /dev/null +++ b/src/mainboard/system76/kbl-u/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/kbl-u/ramstage.c b/src/mainboard/system76/kbl-u/ramstage.c new file mode 100644 index 0000000000..43ee54f50a --- /dev/null +++ b/src/mainboard/system76/kbl-u/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <mainboard/gpio.h> + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/system76/kbl-u/romstage.c b/src/mainboard/system76/kbl-u/romstage.c new file mode 100644 index 0000000000..c55978e05f --- /dev/null +++ b/src/mainboard/system76/kbl-u/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->CaVrefConfig = 2; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/data.vbt b/src/mainboard/system76/kbl-u/variants/galp3-b/data.vbt Binary files differnew file mode 100644 index 0000000000..92bd9813dc --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/data.vbt diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c new file mode 100644 index 0000000000..a7c927f82a --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x15581414, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581414), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb b/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb new file mode 100644 index 0000000000..134fbec7a7 --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/skylake + device domain 0 on + subsystemid 0x1558 0x1413 inherit + end +end |