diff options
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 22 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 3 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h | 26 |
3 files changed, 48 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 3e33053abb..4909ea4ccb 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -196,6 +196,13 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SendVrMbxCmd = config->SendVrMbxCmd; + /* Acoustic Noise Mitigation */ + params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; + params->SlowSlewRateForIa = config->SlowSlewRateForIa; + params->SlowSlewRateForGt = config->SlowSlewRateForGt; + params->SlowSlewRateForSa = config->SlowSlewRateForSa; + params->FastPkgCRampDisable = config->FastPkgCRampDisable; + soc_irq_settings(params); } @@ -801,6 +808,21 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, fsp_display_upd_value("SendVrMbxCmd", 1, original->SendVrMbxCmd, params->SendVrMbxCmd); + fsp_display_upd_value("AcousticNoiseMitigation", 1, + original->AcousticNoiseMitigation, + params->AcousticNoiseMitigation); + fsp_display_upd_value("SlowSlewRateForIa", 1, + original->SlowSlewRateForIa, + params->SlowSlewRateForIa); + fsp_display_upd_value("SlowSlewRateForGt", 1, + original->SlowSlewRateForGt, + params->SlowSlewRateForGt); + fsp_display_upd_value("SlowSlewRateForSa", 1, + original->SlowSlewRateForSa, + params->SlowSlewRateForSa); + fsp_display_upd_value("FastPkgCRampDisable", 1, + original->FastPkgCRampDisable, + params->FastPkgCRampDisable); } static void pci_set_subsystem(device_t dev, unsigned int vendor, diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4db8382d68..a7804af14f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -485,6 +485,9 @@ struct soc_intel_skylake_config { * 0b - Enabled * 1b - Disabled */ + /* FSP 1.1 */ + u8 FastPkgCRampDisable; + /* FSP 2.0 */ u8 FastPkgCRampDisableIa; u8 FastPkgCRampDisableGt; u8 FastPkgCRampDisableSa; diff --git a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h index 45f2099a38..32b926a6d4 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -950,14 +950,34 @@ typedef struct { UINT8 Early8254ClockGatingEnable; /** Offset 0x03E5 - Enable VR specific mailbox command - When set, an extra VR mailbox command specifically for the MPS IMPV8 VR will be sent. This for FSP only. 0 - Don't Send, 1 - Send + VR specific mailbox commands, 000b: no VR specific command sent, 001b: A VR mailbox command specifically for the MPS IMPV8 VR will be sent, 010b: VR specific command sent for PS4 exit issue, 011b: VR specific command sent for both MPS IMPV8 & PS4 exit issue. $EN_DIS **/ UINT8 SendVrMbxCmd; /** Offset 0x03E6 **/ - UINT8 ReservedSiliconInitUpd[20]; + UINT8 AcousticNoiseMitigation; + +/** Offset 0x03E7 +**/ + UINT8 SlowSlewRateForIa; + +/** Offset 0x03E8 +**/ + UINT8 SlowSlewRateForGt; + +/** Offset 0x03E9 +**/ + UINT8 SlowSlewRateForSa; + +/** Offset 0x03EA +**/ + UINT8 FastPkgCRampDisable; + +/** Offset 0x03EB +**/ + UINT8 ReservedSiliconInitUpd[15]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x244450554C4B5324 /* '$SKLUPD$' */ |