diff options
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/smi.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/smi/smi_util.c | 24 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/smi.h | 3 |
3 files changed, 28 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/smi.h b/src/soc/amd/common/block/include/amdblocks/smi.h index b870f16cdb..6995bef0f3 100644 --- a/src/soc/amd/common/block/include/amdblocks/smi.h +++ b/src/soc/amd/common/block/include/amdblocks/smi.h @@ -48,5 +48,7 @@ void disable_gevent_smi(uint8_t gevent); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void clear_all_smi_status(void); void clear_smi_sci_status(void); +void reset_psp_smi(void); +void configure_psp_smi(void); #endif /* AMD_BLOCK_SMI_H */ diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c index ac2f4b450c..8ec900f762 100644 --- a/src/soc/amd/common/block/smi/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -154,3 +154,27 @@ void clear_smi_sci_status(void) { smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); } + +static void clear_psp_smi(void) +{ + uint32_t reg32; + /* SMITYPE_PSP is 33, so it's bit 33 % 32 in the second 32 bit SMI status register */ + reg32 = smi_read32(SMI_REG_SMISTS1); + reg32 |= 1 << (SMITYPE_PSP % 32); + smi_write32(SMI_REG_SMISTS1, reg32); +} + +void reset_psp_smi(void) +{ + uint32_t reg32; + reg32 = smi_read32(SMI_REG_SMITRIG0); + reg32 &= ~SMITRIG0_PSP; + smi_write32(SMI_REG_SMITRIG0, reg32); +} + +void configure_psp_smi(void) +{ + clear_psp_smi(); + reset_psp_smi(); + configure_smi(SMITYPE_PSP, SMI_MODE_SMI); +} diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index ccdd3c5581..2a847aa104 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -71,7 +71,7 @@ #define SMITYPE_ESPI_SYS 26 #define SMITYPE_ESPI_WAKE_PME 27 /* 28-32 Reserved */ -#define SMITYPE_FCH_FAKE0 33 +#define SMITYPE_PSP 33 #define SMITYPE_FCH_FAKE1 34 #define SMITYPE_FCH_FAKE2 35 /* 36 Reserved */ @@ -163,6 +163,7 @@ #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 +# define SMITRIG0_PSP BIT(25) # define SMITRG0_EOS BIT(28) # define SMI_TIMER_SEL BIT(29) # define SMITRG0_SMIENB BIT(31) |