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-rw-r--r--src/soc/intel/xeon_sp/Makefile.mk3
-rw-r--r--src/soc/intel/xeon_sp/ibl/Makefile.mk7
-rw-r--r--src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h9
-rw-r--r--src/soc/intel/xeon_sp/ibl/include/soc/gpio_soc_defs.h385
-rw-r--r--src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h18
-rw-r--r--src/soc/intel/xeon_sp/ibl/include/soc/pmc.h56
-rw-r--r--src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h9
-rw-r--r--src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h13
-rw-r--r--src/soc/intel/xeon_sp/ibl/lockdown.c18
-rw-r--r--src/soc/intel/xeon_sp/ibl/soc_gpio.c190
-rw-r--r--src/soc/intel/xeon_sp/ibl/soc_pch.c84
-rw-r--r--src/soc/intel/xeon_sp/ibl/soc_pmutil.c102
12 files changed, 892 insertions, 2 deletions
diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk
index 4f87367c5e..1f68f27876 100644
--- a/src/soc/intel/xeon_sp/Makefile.mk
+++ b/src/soc/intel/xeon_sp/Makefile.mk
@@ -5,8 +5,7 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg
subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg
subdirs-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += spr ebg
-## TODO: GNR IBL codes are initially reused from EBG, will update later.
-subdirs-$(CONFIG_SOC_INTEL_GRANITERAPIDS) += gnr ebg
+subdirs-$(CONFIG_SOC_INTEL_GRANITERAPIDS) += gnr ibl
bootblock-y += bootblock.c spi.c lpc.c pch.c report_platform.c
romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c
diff --git a/src/soc/intel/xeon_sp/ibl/Makefile.mk b/src/soc/intel/xeon_sp/ibl/Makefile.mk
new file mode 100644
index 0000000000..a92d559827
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += soc_gpio.c soc_pch.c
+romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c
+ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ibl/include
diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h b/src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h
new file mode 100644
index 0000000000..911ff15203
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DEVICE_AZALIA_H
+#define DEVICE_AZALIA_H
+
+#define HDA_PCS 0x54
+#define HDA_PCS_PS_D3HOT 3
+
+#endif /* DEVICE_AZALIA_H */
diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/ibl/include/soc/gpio_soc_defs.h
new file mode 100644
index 0000000000..96fd749419
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/include/soc/gpio_soc_defs.h
@@ -0,0 +1,385 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef IBL_GPIO_DEFS_H
+#define IBL_GPIO_DEFS_H
+
+#ifndef __ACPI__
+#include <stddef.h>
+#endif
+
+/* GPIO Community 0 */
+#define COMM_0 0
+#define GPPC_A 0x0
+#define GPPC_B 0x1
+#define GPPC_S 0x2
+/* GPIO Community 1 */
+#define COMM_1 1
+#define GPPC_C 0x3
+#define GPP_D 0x4
+/* GPIO Community 3 */
+#define COMM_3 2
+#define GPP_E 0x5
+/* GPIO Community 4 */
+#define COMM_4 3
+#define GPPC_H 0x6
+#define GPPC_J 0x7
+/* GPIO Community 5 */
+#define COMM_5 4
+#define GPP_I 0x8
+#define GPP_L 0x9
+#define GPP_M 0xA
+#define GPP_N 0xB
+/* GPIO Community 2 */
+#define COMM_2 5
+#define GPP_O 0xC
+
+#define GPIO_MAX_NUM_PER_GROUP 24
+
+/* Group A */
+#define GPPC_A0 0
+#define GPPC_A1 1
+#define GPPC_A2 2
+#define GPPC_A3 3
+#define GPPC_A4 4
+#define GPPC_A5 5
+#define GPPC_A6 6
+#define GPPC_A7 7
+#define GPPC_A8 8
+#define GPPC_A9 9
+#define GPPC_A10 10
+#define GPPC_A11 11
+#define GPPC_A12 12
+#define GPPC_A13 13
+#define GPPC_A14 14
+#define GPPC_A15 15
+#define GPPC_A16 16
+#define GPPC_A17 17
+#define GPPC_A18 18
+#define GPPC_A19 19
+#define ESPI_CLK_LOOPBK 20
+
+/* Group B */
+#define GPPC_B0 21
+#define GPPC_B1 22
+#define GPPC_B2 23
+#define GPPC_B3 24
+#define GPPC_B4 25
+#define GPPC_B5 26
+#define GPPC_B6 27
+#define GPPC_B7 28
+#define GPPC_B8 29
+#define GPPC_B9 30
+#define GPPC_B10 31
+#define GPPC_B11 32
+#define GPPC_B12 33
+#define GPPC_B13 34
+#define GPPC_B14 35
+#define GPPC_B15 36
+#define GPPC_B16 37
+#define GPPC_B17 38
+#define GPPC_B18 39
+#define GPPC_B19 40
+#define GPPC_B20 41
+#define GPPC_B21 42
+#define GPPC_B22 43
+#define GPPC_B23 44
+
+/*
+ * Order 45-52 belongs to fields which are not described in EDS but
+ * can be found while using Cscript. Keep the order here to make GPIO
+ * table can be set as expected.
+ */
+
+/* Group S */
+#define GPPC_S0 53
+#define GPPC_S1 54
+#define GPPC_S2 55
+#define GPPC_S3 56
+#define GPPC_S4 57
+#define GPPC_S5 58
+#define GPPC_S6 59
+#define GPPC_S7 60
+#define GPPC_S8 61
+#define GPPC_S9 62
+#define GPPC_S10 63
+#define GPPC_S11 64
+#define SPI_CLK_LOOPBK 65
+
+#define NUM_GPIO_COM0_PADS (SPI_CLK_LOOPBK - GPPC_A0 + 1)
+
+/* Community 1 */
+/* Group C */
+#define GPPC_C0 66
+#define GPPC_C1 67
+#define GPPC_C2 68
+#define GPPC_C3 69
+#define GPPC_C4 70
+#define GPPC_C5 71
+#define GPPC_C6 72
+#define GPPC_C7 73
+#define GPPC_C8 74
+#define GPPC_C9 75
+#define GPPC_C10 76
+#define GPPC_C11 77
+#define GPPC_C12 78
+#define GPPC_C13 79
+#define GPPC_C14 80
+#define GPPC_C15 81
+#define GPPC_C16 82
+#define GPPC_C17 83
+#define GPPC_C18 84
+#define GPPC_C19 85
+#define GPPC_C20 86
+#define GPPC_C21 87
+
+/* Group D */
+#define GPP_D0 88
+#define GPP_D1 89
+#define GPP_D2 90
+#define GPP_D3 91 // Not described in EDS
+#define GPP_D4 92 // Not described in EDS
+#define GPP_D5 93 // Not described in EDS
+#define GPP_D6 94
+#define GPP_D7 95
+#define GPP_D8 96
+#define GPP_D9 97
+#define GPP_D10 98
+#define GPP_D11 99
+#define GPP_D12 100
+#define GPP_D13 101
+#define GPP_D14 102
+#define GPP_D15 103
+#define GPP_D16 104
+#define GPP_D17 105
+#define GPP_D18 106
+#define GPP_D19 107
+#define GPP_D20 108
+#define GPP_D21 109
+#define GPP_D22 110
+#define GPP_D23 111
+
+#define NUM_GPIO_COM1_PADS (GPP_D23 - GPPC_C0 + 1)
+
+/* Community 3 */
+/* Group E */
+#define GPP_E0 112
+#define GPP_E1 113
+#define GPP_E2 114
+#define GPP_E3 115
+#define GPP_E4 116
+#define GPP_E5 117
+#define GPP_E6 118
+#define GPP_E7 119
+#define GPP_E8 120
+#define GPP_E9 121
+#define GPP_E10 122
+#define GPP_E11 123
+#define GPP_E12 124
+#define GPP_E13 125
+#define GPP_E14 126
+#define GPP_E15 127
+#define GPP_E16 128
+#define GPP_E17 129
+#define GPP_E18 130
+#define GPP_E19 131
+#define GPP_E20 132 // Not described in EDS
+#define GPP_E21 133 // Not described in EDS
+#define GPP_E22 134 // Not described in EDS
+#define GPP_E23 135 // Not described in EDS
+
+#define NUM_GPIO_COM3_PADS (GPP_E23 - GPP_E0 + 1)
+
+/* Community 4 */
+/* Group H */
+#define GPPC_H0 136
+#define GPPC_H1 137
+#define GPPC_H2 138 // Not described in EDS
+#define GPPC_H3 139 // Not described in EDS
+#define GPPC_H4 140 // Not described in EDS
+#define GPPC_H5 141 // Not described in EDS
+#define GPPC_H6 142
+#define GPPC_H7 143
+#define GPPC_H8 144 // Not described in EDS
+#define GPPC_H9 145 // Not described in EDS
+#define GPPC_H10 146 // Not described in EDS
+#define GPPC_H11 147 // Not described in EDS
+#define GPPC_H12 148 // Not described in EDS
+#define GPPC_H13 149 // Not described in EDS
+#define GPPC_H14 150 // Not described in EDS
+#define GPPC_H15 151
+#define GPPC_H16 152
+#define GPPC_H17 153
+#define GPPC_H18 154
+#define GPPC_H19 155
+
+/* Group J */
+#define GPP_J0 156
+#define GPP_J1 157
+#define GPP_J2 158
+#define GPP_J3 159
+#define GPP_J4 160
+#define GPP_J5 161
+#define GPP_J6 162
+#define GPP_J7 163
+#define GPP_J8 164
+#define GPP_J9 165 // Not described in EDS
+#define GPP_J10 166 // Not described in EDS
+#define GPP_J11 167 // Not described in EDS
+#define GPP_J12 168
+#define GPP_J13 169
+#define GPP_J14 170
+#define GPP_J15 171
+#define GPP_J16 172 // Not described in EDS
+#define GPP_J17 173 // Not described in EDS
+
+#define NUM_GPIO_COM4_PADS (GPP_J17 - GPPC_H0 + 1)
+
+/* Community 5 */
+/* Group I */
+#define GPP_I0 180 // Not described in EDS
+#define GPP_I1 181 // Not described in EDS
+#define GPP_I2 182 // Not described in EDS
+#define GPP_I3 183 // Not described in EDS
+#define GPP_I4 184 // Not described in EDS
+#define GPP_I5 185 // Not described in EDS
+#define GPP_I6 186 // Not described in EDS
+#define GPP_I7 187 // Not described in EDS
+#define GPP_I8 188 // Not described in EDS
+#define GPP_I9 189 // Not described in EDS
+#define GPP_I10 190 // Not described in EDS
+#define GPP_I11 191 // Not described in EDS
+#define GPP_I12 192
+#define GPP_I13 193
+#define GPP_I14 194
+#define GPP_I15 195
+#define GPP_I16 196
+#define GPP_I17 197
+#define GPP_I18 198 // Not described in EDS
+#define GPP_I19 199 // Not described in EDS
+#define GPP_I20 200 // Not described in EDS
+#define GPP_I21 201
+#define GPP_I22 202
+#define GPP_I23 203
+
+/* Group L */
+#define GPP_L0 204
+#define GPP_L1 205
+#define GPP_L2 206
+#define GPP_L3 207
+#define GPP_L4 208
+#define GPP_L5 209
+#define GPP_L6 210
+#define GPP_L7 211
+#define GPP_L8 212
+#define GPP_L9 213 // Not described in EDS
+#define GPP_L10 214 // Not described in EDS
+#define GPP_L11 215 // Not described in EDS
+#define GPP_L12 216 // Not described in EDS
+#define GPP_L13 217 // Not described in EDS
+#define GPP_L14 218 // Not described in EDS
+#define GPP_L15 219 // Not described in EDS
+#define GPP_L16 220 // Not described in EDS
+#define GPP_L17 221 // Not described in EDS
+
+/* Group M */
+#define GPP_M0 222
+#define GPP_M1 223
+#define GPP_M2 224
+#define GPP_M3 225
+#define GPP_M4 226
+#define GPP_M5 227
+#define GPP_M6 228
+#define GPP_M7 229
+#define GPP_M8 230
+#define GPP_M9 231 // Not described in EDS
+#define GPP_M10 232 // Not described in EDS
+#define GPP_M11 233
+#define GPP_M12 234
+#define GPP_M13 235 // Not described in EDS
+#define GPP_M14 236 // Not described in EDS
+#define GPP_M15 237
+#define GPP_M16 238
+#define GPP_M17 239
+
+/* Group N */
+#define GPP_N0 240 // Not described in EDS
+#define GPP_N1 241
+#define GPP_N2 242 // Not described in EDS
+#define GPP_N3 243 // Not described in EDS
+#define GPP_N4 244
+#define GPP_N5 245 // Not described in EDS
+#define GPP_N6 246 // Not described in EDS
+#define GPP_N7 247 // Not described in EDS
+#define GPP_N8 248 // Not described in EDS
+#define GPP_N9 249 // Not described in EDS
+#define GPP_N10 250 // Not described in EDS
+#define GPP_N11 251 // Not described in EDS
+#define GPP_N12 252 // Not described in EDS
+#define GPP_N13 253 // Not described in EDS
+#define GPP_N14 254 // Not described in EDS
+#define GPP_N15 255 // Not described in EDS
+#define GPP_N16 256 // Not described in EDS
+#define GPP_N17 257 // Not described in EDS
+
+#define NUM_GPIO_COM5_PADS (GPP_N17 - GPP_I0 + 1)
+
+/* Community 2 */
+/* Group O */
+#define GPP_O0 258
+#define GPP_O1 259
+#define GPP_O2 260
+#define GPP_O3 261
+#define GPP_O4 262
+#define GPP_O5 263
+#define GPP_O6 264
+#define GPP_O7 265
+#define GPP_O8 266
+#define GPP_O9 267
+#define GPP_O10 268
+#define GPP_O11 269
+#define GPP_O12 270
+#define GPP_O13 271
+#define GPP_O14 272
+#define GPP_O15 273
+#define GPP_O16 274
+
+#define NUM_GPIO_COM2_PADS (GPP_O16 - GPP_O0 + 1)
+
+#define TOTAL_PADS (GPP_O16 + 1)
+
+#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n) \
+ (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
+#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
+#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
+#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
+
+#define NUM_GPI_STATUS_REGS \
+ ((NUM_GPIO_COM0_GPI_REGS) + \
+ (NUM_GPIO_COM1_GPI_REGS) + \
+ (NUM_GPIO_COM3_GPI_REGS) + \
+ (NUM_GPIO_COM4_GPI_REGS) + \
+ (NUM_GPIO_COM5_GPI_REGS) + \
+ (NUM_GPIO_COM2_GPI_REGS))
+
+/* Register defines */
+#define GPIO_MISCCFG 0x10
+
+#define HOSTSW_OWN_REG_0 0x130
+#define PAD_CFG_BASE 0x700
+#define GPI_INT_STS_0 0x200
+#define GPI_INT_EN_0 0x210
+#define GPI_SMI_STS_0 0x270
+#define GPI_SMI_EN_0 0x290
+
+#define PAD_CFG_LOCK_A 0x100
+#define PAD_CFG_LOCK_B 0x108
+#define PAD_CFG_LOCK_C 0x100
+#define PAD_CFG_LOCK_D 0x108
+
+#endif /* IBL_GPIO_DEFS_H */
diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h
new file mode 100644
index 0000000000..d8ee4e0e78
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _PCR_IDS_H_
+#define _PCR_IDS_H_
+
+#define PID_CSME0 0x90
+#define PID_ITSS 0xC4
+#define PID_RTC 0xC3
+#define PID_PSF3 0xBC
+#define PID_DMI 0x88
+#define PID_GPIOCOM5 0x69
+#define PID_GPIOCOM4 0x6a
+#define PID_GPIOCOM3 0x6b
+#define PID_GPIOCOM2 0x6c
+#define PID_GPIOCOM1 0x6d
+#define PID_GPIOCOM0 0x6e
+
+#endif /* _PCR_IDS_H_ */
diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h b/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h
new file mode 100644
index 0000000000..59c2d73bd2
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_PMC_H_
+#define _SOC_PMC_H_
+
+/* PCI Configuration Space (D31:F2): PMC */
+#define PWRMBASE 0x10
+#define ABASE 0x20
+/* Memory mapped IO registers in PMC */
+#define GEN_PMCON_A 0x1020
+#define GBL_RST_STS (1 << 24)
+#define DISB (1 << 23)
+#define MS4V (1 << 18)
+#define SUS_PWR_FLR (1 << 16)
+#define PWR_FLR (1 << 14)
+#define HOST_RST_STS (1 << 9)
+#define PER_SMI_SEL_MASK (3 << 1)
+#define SMI_RATE_64S (0 << 1)
+#define SMI_RATE_32S (1 << 1)
+#define SMI_RATE_16S (2 << 1)
+#define SMI_RATE_8S (3 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+#define GEN_PMCON_B 0x1024
+#define SLP_STR_POL_LOCK (1 << 18)
+#define SMI_LOCK (1 << 4)
+#define RTC_BATTERY_DEAD (1 << 2)
+#define PM_CFG 0x1818
+#define PMC_LOCK (1 << 27)
+#define PMSYNC_MISC_CFG 0x18c8
+#define PMSYNC_LOCK (1 << 15)
+#define PCH_PWRM_ACPI_TMR_CTL 0x18fc
+#define ACPI_TIM_DIS (1 << 1)
+#define GPIO_GPE_CFG 0x1920
+#define GPE0_DWX_MASK 0xf
+#define GPE0_DW_SHIFT(x) (4 * (x))
+#define GBLRST_CAUSE0 0x1924
+#define GBLRST_CAUSE1 0x1928
+#define ACTL 0x1BD8
+#define PMC_ACPI_CNT 0x1BD8
+#define PWRM_EN (1 << 8)
+#define ACPI_EN (1 << 7)
+#define SCI_IRQ_SEL (7 << 0)
+#define SCI_IRQ_ADJUST 0
+#define SCIS_IRQ9 0
+#define SCIS_IRQ10 1
+#define SCIS_IRQ11 2
+#define SCIS_IRQ20 4
+#define SCIS_IRQ21 5
+#define SCIS_IRQ22 6
+#define SCIS_IRQ23 7
+#define ST_PG_FDIS1 0x1e20
+#define ST_FDIS_LK (1 << 31)
+#define NST_PG_FDIS1 0x1e28
+#define NST_FDIS_DSP (1 << 23)
+
+#endif
diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h
new file mode 100644
index 0000000000..acb1785293
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_SOC_PCH_H_
+#define _SOC_SOC_PCH_H_
+
+void pch_lock_dmictl(void);
+void pch_disable_hda(void);
+
+#endif /* _SOC_SOC_PCH_H_ */
diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h
new file mode 100644
index 0000000000..1cb36f426a
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_IBL_PM_H_
+#define _SOC_IBL_PM_H_
+
+#define GPE0_STS(x) (0x60 + ((x) * 4))
+#define GPE0_EN(x) (0x70 + ((x) * 4))
+
+/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */
+#define ETR 0x1048
+#define PRSTS 0x1810
+
+#endif /* _SOC_IBL_PM_H_ */
diff --git a/src/soc/intel/xeon_sp/ibl/lockdown.c b/src/soc/intel/xeon_sp/ibl/lockdown.c
new file mode 100644
index 0000000000..694e4a24a3
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/lockdown.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/cfg.h>
+#include <intelblocks/fast_spi.h>
+#include <intelpch/lockdown.h>
+#include <soc/lockdown.h>
+
+void sata_lockdown_config(int chipset_lockdown)
+{
+}
+
+void spi_lockdown_config(int chipset_lockdown)
+{
+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
+ fast_spi_set_bde();
+ fast_spi_set_vcl();
+ }
+}
diff --git a/src/soc/intel/xeon_sp/ibl/soc_gpio.c b/src/soc/intel/xeon_sp/ibl/soc_gpio.c
new file mode 100644
index 0000000000..826b5e7bb9
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/soc_gpio.c
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+
+/*
+ * Reset mapping
+ * 00 = RSMRST#
+ * 01 = Host Deep Reset
+ * 10 = PLTRST#
+ * 11 = Reserved
+ */
+static const struct reset_mapping rst_map[] = {
+ { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+
+static const struct pad_group emmitsburg_community0_groups[] = {
+ INTEL_GPP(GPPC_A0, GPPC_A0, ESPI_CLK_LOOPBK), /* GPPC A */
+ INTEL_GPP(GPPC_A0, GPPC_B0, GPPC_B23), /* GPPC B */
+ INTEL_GPP(GPPC_A0, GPPC_S0, SPI_CLK_LOOPBK), /* GPPC S */
+};
+
+static const struct pad_group emmitsburg_community1_groups[] = {
+ INTEL_GPP(GPPC_C0, GPPC_C0, GPPC_C21), /* GPPC C */
+ INTEL_GPP(GPPC_C0, GPP_D0, GPP_D23), /* GPP D */
+};
+
+static const struct pad_group emmitsburg_community3_groups[] = {
+ INTEL_GPP(GPP_E0, GPP_E0, GPP_E23), /* GPP E */
+};
+
+static const struct pad_group emmitsburg_community4_groups[] = {
+ INTEL_GPP(GPPC_H0, GPPC_H0, GPPC_H19), /* GPPC H */
+ INTEL_GPP(GPPC_H0, GPP_J0, GPP_J17), /* GPP J */
+};
+
+static const struct pad_group emmitsburg_community5_groups[] = {
+ INTEL_GPP(GPP_I0, GPP_I0, GPP_I23), /* GPP I */
+ INTEL_GPP(GPP_I0, GPP_L0, GPP_L17), /* GPP L */
+ INTEL_GPP(GPP_I0, GPP_M0, GPP_M17), /* GPP M */
+ INTEL_GPP(GPP_I0, GPP_N0, GPP_N17), /* GPP N */
+};
+
+static const struct pad_group emmitsburg_community2_groups[] = {
+ INTEL_GPP(GPP_O0, GPP_O0, GPP_O16), /* GPP O */
+};
+
+static const struct pad_community emmitsburg_gpio_communities[] = {
+ [COMM_0] = { /* GPIO Community 0: GPPC A, B, S */
+ .port = PID_GPIOCOM0,
+ .first_pad = GPPC_A0,
+ .last_pad = SPI_CLK_LOOPBK,
+ .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPIO_COM0",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = emmitsburg_community0_groups,
+ .num_groups = ARRAY_SIZE(emmitsburg_community0_groups),
+ },
+ [COMM_1] = { /* GPIO Community 1: GPPC C, GPP D */
+ .port = PID_GPIOCOM1,
+ .first_pad = GPPC_C0,
+ .last_pad = GPP_D23,
+ .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPIO_COM1",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = emmitsburg_community1_groups,
+ .num_groups = ARRAY_SIZE(emmitsburg_community1_groups),
+ },
+ [COMM_3] = { /* GPIO Community 3: GPP E */
+ .port = PID_GPIOCOM3,
+ .first_pad = GPP_E0,
+ .last_pad = GPP_E23,
+ .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPIO_COM3",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = emmitsburg_community3_groups,
+ .num_groups = ARRAY_SIZE(emmitsburg_community3_groups),
+ },
+ [COMM_4] = { /* GPIO Community 4: GPPC H, J */
+ .port = PID_GPIOCOM4,
+ .first_pad = GPPC_H0,
+ .last_pad = GPP_J17,
+ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPIO_COM4",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = emmitsburg_community4_groups,
+ .num_groups = ARRAY_SIZE(emmitsburg_community4_groups),
+ },
+ [COMM_5] = { /* GPIO Community 5: GPP I, L, M, N */
+ .port = PID_GPIOCOM5,
+ .first_pad = GPP_I0,
+ .last_pad = GPP_N17,
+ .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPIO_COM5",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = emmitsburg_community5_groups,
+ .num_groups = ARRAY_SIZE(emmitsburg_community5_groups),
+ },
+ [COMM_2] = { /* GPIO Community 2: GPP O */
+ .port = PID_GPIOCOM2,
+ .first_pad = GPP_O0,
+ .last_pad = GPP_O16,
+ .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPIO_COM2",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = emmitsburg_community2_groups,
+ .num_groups = ARRAY_SIZE(emmitsburg_community2_groups),
+ },
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+ *num_communities = ARRAY_SIZE(emmitsburg_gpio_communities);
+ return emmitsburg_gpio_communities;
+}
+
+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
+{
+ static const struct pmc_to_gpio_route routes[] = {
+ { GPPC_A, GPPC_A },
+ { GPPC_B, GPPC_B },
+ { GPPC_S, GPPC_S },
+ { GPPC_C, GPPC_C },
+ { GPP_D, GPP_D },
+ { GPP_E, GPP_E },
+ { GPPC_H, GPPC_H },
+ { GPPC_J, GPPC_J },
+ };
+
+ *num = ARRAY_SIZE(routes);
+ return routes;
+}
diff --git a/src/soc/intel/xeon_sp/ibl/soc_pch.c b/src/soc/intel/xeon_sp/ibl/soc_pch.c
new file mode 100644
index 0000000000..a40af7abc7
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/soc_pch.c
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
+#include <intelblocks/p2sb.h>
+#include <soc/azalia_device.h>
+#include <soc/bootblock.h>
+#include <soc/soc_pch.h>
+#include <soc/pch.h>
+#include <soc/pmc.h>
+#include <console/console.h>
+
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x600
+#define PCR_PSFX_TO_SHDW_BAR4 0x10
+#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
+#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
+#define PCR_DMI_MISC_PORT_CFG 0x20D8
+#define MISC_PORT_CFG_LOCK BIT(23)
+#define PCR_DMI_DMICTL 0x2234
+#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
+
+static void soc_config_acpibase(void)
+{
+ uint32_t pmc_reg_value;
+ uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
+
+ pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
+
+ if (pmc_reg_value != 0xffffffff) {
+ /* Disable Io Space before changing the address */
+ pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
+ ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
+ /* Program ABASE in PSF3 PMC space BAR4*/
+ pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
+ ACPI_BASE_ADDRESS);
+ /* Enable IO Space */
+ pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
+ ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
+ }
+ /* Enable Bus Master and IO Space */
+ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_IO | PCI_COMMAND_MASTER));
+
+ uint16_t data = pcr_read16(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
+ printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data);
+}
+
+void bootblock_pch_init(void)
+{
+ /*
+ * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT
+ */
+ soc_config_acpibase();
+}
+
+void pch_lock_dmictl(void)
+{
+ uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
+ pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK);
+ pcr_or32(PID_DMI, PCR_DMI_MISC_PORT_CFG, MISC_PORT_CFG_LOCK);
+}
+
+#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
+#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
+#define PSF3_HDA_BASE_ADDRESS 0x280
+
+void pch_disable_hda(void)
+{
+ /* Ensure memory, io, and bus master are all disabled */
+ pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
+ /* Put controller to D3 */
+ pci_or_config32(PCH_DEV_HDA, HDA_PCS, HDA_PCS_PS_D3HOT);
+ /* Disable DSP in PMC */
+ pmc_or_mmio32(NST_PG_FDIS1, NST_FDIS_DSP);
+ /* Hide PCI function */
+ pcr_or32(PID_PSF3, PSF3_HDA_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
+ PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
+
+ printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__);
+}
diff --git a/src/soc/intel/xeon_sp/ibl/soc_pmutil.c b/src/soc/intel/xeon_sp/ibl/soc_pmutil.c
new file mode 100644
index 0000000000..7160dee791
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/soc_pmutil.c
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Helper functions for dealing with power management registers
+ * and the differences between PCH variants.
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
+#include <soc/pm.h>
+#include <soc/pmc.h>
+
+uint8_t *pmc_mmio_regs(void)
+{
+ /* PMC PWRMBASE can be hidden after FSP-S so can't be accessed using PCI CSR,
+ * hence use hard-coded address */
+ return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
+}
+
+uintptr_t soc_read_pmc_base(void)
+{
+ return (uintptr_t)(pmc_mmio_regs());
+}
+
+uint32_t *soc_pmc_etr_addr(void)
+{
+ /*
+ * The pointer returned must not be cached, because the address depends on the
+ * MMCONF base address and the assigned PCI bus number, which both may change
+ * during the boot process!
+ */
+ return (uint32_t *)(soc_read_pmc_base() + ETR);
+}
+
+int soc_get_rtc_failed(void)
+{
+ uint32_t pmcon_b = read32(pmc_mmio_regs() + GEN_PMCON_B);
+ int rtc_fail = !!(pmcon_b & RTC_BATTERY_DEAD);
+
+ if (rtc_fail)
+ printk(BIOS_ERR, "%s: RTC battery dead or removed\n", __func__);
+
+ return rtc_fail;
+}
+
+void soc_fill_power_state(struct chipset_power_state *ps)
+{
+ uint8_t *pmc;
+
+ pmc = pmc_mmio_regs();
+
+ ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
+ ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
+ ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
+ ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
+
+ printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b);
+
+ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0],
+ ps->gblrst_cause[1]);
+}
+
+/*
+ * Set which power state system will be after reapplying
+ * the power (from G3 State)
+ */
+void pmc_soc_set_afterg3_en(const bool on)
+{
+ uint8_t reg8;
+ uint8_t *const pmcbase = pmc_mmio_regs();
+
+ reg8 = read8(pmcbase + GEN_PMCON_A);
+ if (on)
+ reg8 &= ~SLEEP_AFTER_POWER_FAIL;
+ else
+ reg8 |= SLEEP_AFTER_POWER_FAIL;
+ write8(pmcbase + GEN_PMCON_A, reg8);
+}
+
+void pmc_lock_smi(void)
+{
+ printk(BIOS_DEBUG, "Locking SMM enable.\n");
+ pmc_or_mmio32(GEN_PMCON_B, SMI_LOCK);
+}
+
+void pmc_lockdown_config(void)
+{
+ /* PMSYNC */
+ pmc_or_mmio32(PMSYNC_MISC_CFG, PMSYNC_LOCK);
+
+ /* Make sure payload/OS can't trigger global reset */
+ pmc_global_reset_disable_and_lock();
+
+ /* Lock PMC stretch policy */
+ pmc_or_mmio32(GEN_PMCON_B, SLP_STR_POL_LOCK);
+ pmc_or_mmio32(ST_PG_FDIS1, ST_FDIS_LK);
+ pmc_or_mmio32(PM_CFG, PMC_LOCK);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 17:39:34 +0000