diff options
| -rw-r--r-- | src/drivers/genesyslogic/gl9763e/Kconfig | 8 | ||||
| -rw-r--r-- | src/drivers/genesyslogic/gl9763e/gl9763e.c | 5 | ||||
| -rw-r--r-- | src/drivers/genesyslogic/gl9763e/gl9763e.h | 1 |
3 files changed, 13 insertions, 1 deletions
diff --git a/src/drivers/genesyslogic/gl9763e/Kconfig b/src/drivers/genesyslogic/gl9763e/Kconfig index c254707f66..555ad91d0e 100644 --- a/src/drivers/genesyslogic/gl9763e/Kconfig +++ b/src/drivers/genesyslogic/gl9763e/Kconfig @@ -1,2 +1,8 @@ config DRIVERS_GENESYSLOGIC_GL9763E - bool + bool "Genesys Logic GL9763E" + default n + +config DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX + bool "Set L1 entry delay to MAX" + depends on DRIVERS_GENESYSLOGIC_GL9763E + default n diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c index 4dcfbdcbd0..a4842e81c3 100644 --- a/src/drivers/genesyslogic/gl9763e/gl9763e.c +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c @@ -23,6 +23,11 @@ static void gl9763e_init(struct device *dev) pci_or_config32(dev, SCR, SCR_AXI_REQ); /* Disable L0s support */ pci_and_config32(dev, CFG_REG_2, ~CFG_REG_2_L0S); + + if (CONFIG(DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX)) + /* Set L1 entry delay to MAX */ + pci_or_config32(dev, CFG_REG_2, CFG_REG_2_L1DLY_MAX); + /* Set SSC to 30000 ppm */ pci_update_config32(dev, PLL_CTL_2, ~PLL_CTL_2_MAX_SSC_MASK, MAX_SSC_30000PPM); /* Enable SSC */ diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.h b/src/drivers/genesyslogic/gl9763e/gl9763e.h index 7f5dbf9c05..647920ca95 100644 --- a/src/drivers/genesyslogic/gl9763e/gl9763e.h +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.h @@ -14,6 +14,7 @@ #define CFG_REG_2 0x8A4 #define CFG_REG_2_L0S BIT(11) +#define CFG_REG_2_L1DLY_MAX (0x3FF << 19) #define PLL_CTL 0x938 #define PLL_CTL_SSC BIT(19) |