diff options
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 4e10f3d2de..e6151313ae 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -232,11 +232,17 @@ config MAX_ROOT_PORTS default MAX_PCH_ROOT_PORTS config MAX_PCIE_CLOCK_SRC + prompt "Number of Source Clock supported from SOC" int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N - default 7 if SOC_INTEL_ALDERLAKE_PCH_P default 18 if SOC_INTEL_ALDERLAKE_PCH_S + default 10 if SOC_INTEL_ALDERLAKE_PCH_P + help + With external clock buffer, Alderlake-P can support up to three additional source clocks. + This is done by setting the corresponding GPIO pin(s) to native function to use as + SRCCLK_OE[6..9]. In addition, SRCCLK6 does not need to be set to free running clock. + If any of SRCCLKReq 6..9 is asserted, SRCCLK6 will be turned on. config MAX_PCIE_CLOCK_REQ int |