diff options
| -rw-r--r-- | src/mainboard/getac/p470/cmos.layout | 3 | ||||
| -rw-r--r-- | src/mainboard/getac/p470/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/getac/p470/romstage.c | 7 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/cmos.layout | 3 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/roda/rk886ex/cmos.layout | 3 | ||||
| -rw-r--r-- | src/mainboard/roda/rk886ex/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/roda/rk886ex/romstage.c | 7 |
9 files changed, 32 insertions, 9 deletions
diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index f86e479df5..130f1cefc6 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -93,7 +93,8 @@ entries 416 512 s 0 boot_devices 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded -#937 47 r 0 unused +937 1 e 1 lpt +#938 46 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 26939772ad..2929cbee5b 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -86,7 +86,9 @@ chip northbridge/intel/i945 device pnp 2e.1 off # ACPI PM end # 2e.2 does not exist - device pnp 2e.3 off # Parallel port + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 end device pnp 2e.4 on # COM1 io 0x60 = 0x3f8 diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index ac71a6b256..270a7bd578 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -34,6 +34,7 @@ #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" +#include "option_table.h" void setup_ich7_gpios(void) { @@ -81,12 +82,16 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { + int lpt_en = 0; + if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); // Enable 0x02e0 - 0x2ff pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1); // Enable 0x600 - 0x6ff diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index 6f2647927e..4ae8834cb0 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -104,8 +104,9 @@ entries 968 1 e 2 ethernet1 969 1 e 2 ethernet2 970 1 e 2 ethernet3 +971 1 e 1 lpt -#971 13 r 0 unused +#972 12 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 8acd4c60ff..b848d40001 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -52,7 +52,9 @@ chip northbridge/intel/i945 chip superio/winbond/w83627thg device pnp 2e.0 off # Floppy end - device pnp 2e.1 off # Parport + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 5d773ce636..925c93efe8 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -58,12 +58,16 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { + int lpt_en = 0; + if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // Set COM1/COM2 decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); // Enable HWM at 0xa00 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); // COM3 decode diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout index 475823d68e..c8790789b8 100644 --- a/src/mainboard/roda/rk886ex/cmos.layout +++ b/src/mainboard/roda/rk886ex/cmos.layout @@ -93,7 +93,8 @@ entries 416 512 s 0 boot_devices 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded -#937 47 r 0 unused +937 1 e 1 lpt +#938 46 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 8762955b60..a139e25966 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -83,7 +83,9 @@ chip northbridge/intel/i945 #device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47n227 - device pnp 2e.1 off # Parallel port + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 end device pnp 2e.2 on # COM1 io 0x60 = 0x3f8 diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index cf36c7cda7..fce53da167 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -36,6 +36,7 @@ #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" +#include "option_table.h" void setup_ich7_gpios(void) { @@ -68,12 +69,16 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { + int lpt_en = 0; + if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); // Enable 0x02e0 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); |