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-rw-r--r--src/mainboard/apple/macbook21/romstage.c5
-rw-r--r--src/mainboard/asrock/g41c-gs/romstage.c3
-rw-r--r--src/mainboard/asus/p5gc-mx/romstage.c5
-rw-r--r--src/mainboard/asus/p5qpl-am/romstage.c2
-rw-r--r--src/mainboard/foxconn/d41s/romstage.c4
-rw-r--r--src/mainboard/foxconn/g41s-k/romstage.c3
-rw-r--r--src/mainboard/getac/p470/romstage.c4
-rw-r--r--src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c5
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/romstage.c2
-rw-r--r--src/mainboard/ibase/mb899/romstage.c1
-rw-r--r--src/mainboard/intel/d510mo/romstage.c4
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c6
-rw-r--r--src/mainboard/intel/dg41wv/romstage.c2
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c5
-rw-r--r--src/mainboard/lenovo/t60/romstage.c4
-rw-r--r--src/mainboard/lenovo/thinkcentre_a58/romstage.c2
-rw-r--r--src/mainboard/lenovo/x60/romstage.c4
-rw-r--r--src/mainboard/lenovo/z61t/romstage.c4
-rw-r--r--src/mainboard/roda/rk886ex/romstage.c5
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.c80
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h15
21 files changed, 94 insertions, 71 deletions
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index a538e0f3e2..fe16fdd37e 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -167,9 +167,7 @@ static void rcba_config(void)
RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN
- | FD_ACMOD | FD_ACAUD;
- RCBA32(FD) |= (1 << 0); /* Required. */
+ RCBA32(FD) |= FD_INTLAN;
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
@@ -217,7 +215,6 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index e0246a88a4..e5e1110591 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -69,8 +69,7 @@ static void mb_lpc_setup(void)
reg32 = RCBA32(GCS);
reg32 |= (1 << 5);
RCBA32(GCS) = reg32;
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | 1;
+
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 6f41b4ccc0..41e87b2a00 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -120,10 +120,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | 1;
-
/* Enable PCIe Root Port Clock Gate */
RCBA32(CG) = 0x00000001;
}
@@ -167,7 +163,6 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index 96473bbcc5..2c1b586a4a 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -123,8 +123,6 @@ static void mb_lpc_setup(void)
reg32 = RCBA32(GCS);
reg32 |= (1 << 5);
RCBA32(GCS) = reg32;
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | 1;
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c
index 2d64bef8c0..194bd7373e 100644
--- a/src/mainboard/foxconn/d41s/romstage.c
+++ b/src/mainboard/foxconn/d41s/romstage.c
@@ -75,10 +75,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
-
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | FD_PATA;
- RCBA32(FD) |= 1;
}
void mainboard_romstage_entry(unsigned long bist)
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index 5ea41ea194..a695c53505 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -66,8 +66,7 @@ static void mb_lpc_setup(void)
RCBA8(OIC) = 0x03;
RCBA8(OIC);
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN |
- FD_ACMOD | FD_ACAUD | FD_PATA | 1;
+ RCBA32(FD) |= FD_INTLAN;
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 18d856b856..820a333184 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -165,8 +165,7 @@ static void rcba_config(void)
RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
- RCBA32(FD) |= (1 << 0); // Required.
+ RCBA32(FD) |= FD_INTLAN;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
@@ -221,7 +220,6 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index 6c1da82af9..acf57445bb 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -83,10 +83,6 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- /* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3
- | FD_ACMOD | FD_ACAUD | 1;
-
/* Enable PCIe Root Port Clock Gate */
RCBA32(CG) = 0x00000001;
}
@@ -130,7 +126,6 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 4613c14d3a..78be08b3ba 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -101,8 +101,6 @@ static void mb_gpio_init(void)
RCBA8(OIC);
RCBA32(GCS) = 0x00190464;
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | 1;
RCBA32(CG) = 0x00000000;
RCBA32(0x3430) = 0x00000001;
RCBA32(0x3e00) = 0xff000001;
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 24bd8a2394..3f52f6ca28 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -185,7 +185,6 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 459fb196d8..8d5224e19f 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -83,9 +83,7 @@ static void rcba_config(void)
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD
- | FD_PATA;
- RCBA32(FD) |= 1;
+ RCBA32(FD) |= FD_INTLAN;
}
void mainboard_romstage_entry(unsigned long bist)
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 6f0e419b76..9a4e0675b6 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -62,10 +62,7 @@ static void rcba_config(void)
RCBA8(OIC) = 0x03;
/* Disable unused devices */
- // FIXME devicetree disables pcie3 not 2.
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE2 | (1 << 10) | FD_INTLAN
- | FD_ACMOD | FD_ACAUD;
- RCBA32(FD) |= 1;
+ RCBA32(FD) |= FD_INTLAN;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
@@ -110,7 +107,6 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index 6e9d034b88..830bc73d75 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -59,8 +59,6 @@ static void mb_lpc_setup(void)
reg32 = RCBA32(GCS);
reg32 |= (1 << 5);
RCBA32(GCS) = reg32;
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | FD_PATA |1;
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 144872d4f2..e85135bfc6 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -166,7 +166,7 @@ static void early_superio_config_w83627thg(void)
static void rcba_config(void)
{
- u32 reg32;
+ u32 reg32 = 0;
/* Set up virtual channel 0 */
@@ -199,9 +199,6 @@ static void rcba_config(void)
int port_shuffle = 0;
/* Disable unused devices */
- reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;
- reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
-
if (read_option(ethernet1, 0) != 0) {
printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");
reg32 |= FD_PCIE1;
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 3b806f9c3b..44ac585721 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -98,8 +98,7 @@ static void rcba_config(void)
RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
- RCBA32(FD) |= (1 << 0); // Required.
+ RCBA32(FD) |= FD_INTLAN;
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
@@ -149,7 +148,6 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
index 149a45d4c1..6d0bc97f10 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -46,8 +46,6 @@ static void mb_lpc_setup(void)
reg32 = RCBA32(GCS);
reg32 |= (1 << 5);
RCBA32(GCS) = reg32;
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
- | FD_ACAUD | 1;
RCBA32(CG) = 0x00000001;
}
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index d6674fe7bf..9c5930ebb1 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -97,8 +97,7 @@ static void rcba_config(void)
RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
- RCBA32(FD) |= (1 << 0); // Required.
+ RCBA32(FD) |= FD_INTLAN;
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
@@ -148,7 +147,6 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index 20dbaba34a..ed0cc7606a 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -98,8 +98,7 @@ static void rcba_config(void)
RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
- RCBA32(FD) |= (1 << 0); // Required.
+ RCBA32(FD) |= FD_INTLAN;
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
@@ -149,7 +148,6 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 6e9cc835ec..1b16266c43 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -133,9 +133,7 @@ static void rcba_config(void)
RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
- FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
- RCBA32(FD) |= (1 << 0); /* Required. */
+ RCBA32(FD) |= FD_INTLAN;
/* This should probably go into the ACPI OS Init trap */
@@ -187,7 +185,6 @@ static void early_ich7_init(void)
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c
index eb0583feed..a93d913a6d 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.c
+++ b/src/southbridge/intel/i82801gx/i82801gx.c
@@ -20,22 +20,86 @@
#include "i82801gx.h"
#include "sata.h"
+static void ich_hide_devfn(unsigned int devfn)
+{
+ switch (devfn) {
+ case PCI_DEVFN(27, 0): /* HD Audio Controller */
+ RCBA32_OR(FD, FD_HDAUD);
+ break;
+ case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
+ case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
+ case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
+ case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
+ case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
+ case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
+ RCBA32_OR(FD, ICH_DISABLE_PCIE(PCI_FUNC(devfn)));
+ break;
+ case PCI_DEVFN(29, 0): /* UHCI #1 */
+ case PCI_DEVFN(29, 1): /* UHCI #2 */
+ case PCI_DEVFN(29, 2): /* UHCI #3 */
+ case PCI_DEVFN(29, 3): /* UHCI #4 */
+ RCBA32_OR(FD, ICH_DISABLE_UHCI(PCI_FUNC(devfn)));
+ break;
+ case PCI_DEVFN(29, 7): /* EHCI #1 */
+ RCBA32_OR(FD, FD_EHCI);
+ break;
+ case PCI_DEVFN(30, 2): /* AC Audio */
+ RCBA32_OR(FD, FD_ACAUD);
+ break;
+ case PCI_DEVFN(30, 3): /* AC Modem */
+ RCBA32_OR(FD, FD_ACMOD);
+ break;
+ case PCI_DEVFN(31, 0): /* LPC */
+ RCBA32_OR(FD, FD_LPCB);
+ break;
+ case PCI_DEVFN(31, 1): /* PATA #1 */
+ RCBA32_OR(FD, FD_PATA);
+ break;
+ case PCI_DEVFN(31, 2): /* SATA #1 */
+ RCBA32_OR(FD, FD_SATA);
+ break;
+ case PCI_DEVFN(31, 3): /* SMBUS */
+ RCBA32_OR(FD, FD_SMBUS);
+ break;
+ }
+}
+
void i82801gx_enable(struct device *dev)
{
u32 reg32;
- /* Enable SERR */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ if (!dev->enabled) {
+ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
+
+ /* Ensure memory, io, and bus master are all disabled */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~(PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ pci_write_config32(dev, PCI_COMMAND, reg32);
- if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) {
- printk(BIOS_DEBUG, "Set SATA mode early\n");
- sata_enable(dev);
+ /* Hide this device if possible */
+ ich_hide_devfn(dev->path.pci.devfn);
+ } else {
+ /* Enable SERR */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_SERR;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) {
+ printk(BIOS_DEBUG, "Set SATA mode early\n");
+ sata_enable(dev);
+ }
}
}
+static void i82801gx_init(void *chip_info)
+{
+ /* Disable performance counter */
+ RCBA32_OR(FD, 1);
+}
+
struct chip_operations southbridge_intel_i82801gx_ops = {
CHIP_NAME("Intel ICH7/ICH7-M (82801Gx) Series Southbridge")
- .enable_dev = i82801gx_enable,
+ .enable_dev = i82801gx_enable,
+ .init = i82801gx_init,
};
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 29c8736552..9fd9fd6273 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -68,6 +68,8 @@ int southbridge_detect_s3_resume(void);
#define SEE (1 << 1)
#define PERE (1 << 0)
+#define ICH_PCIE_DEV_SLOT 28
+
/* PCI Configuration Space (D31:F0): LPC */
#define SERIRQ_CNTL 0x64
@@ -227,6 +229,13 @@ int southbridge_detect_s3_resume(void);
#define RPC 0x0224 /* 32bit */
#define RPFN 0x0238 /* 32bit */
+/* Get the function number assigned to a Root Port */
+#define RPFN_FNGET(reg, port) (((reg) >> ((port) * 4)) & 7)
+/* Set the function number for a Root Port */
+#define RPFN_FNSET(port, func) (((func) & 7) << ((port) * 4))
+/* Root Port function number mask */
+#define RPFN_FNMASK(port) (7 << ((port) * 4))
+
#define TRSR 0x1e00 /* 8bit */
#define TRCR 0x1e10 /* 64bit */
#define TWDR 0x1e18 /* 64bit */
@@ -269,16 +278,14 @@ int southbridge_detect_s3_resume(void);
#define FD_PCIE3 (1 << 18)
#define FD_PCIE2 (1 << 17)
#define FD_PCIE1 (1 << 16)
+#define ICH_DISABLE_PCIE(x) (1 << (16 + (x)))
#define FD_EHCI (1 << 15)
#define FD_LPCB (1 << 14)
/* UHCI must be disabled from 4 downwards.
* If UHCI controllers get disabled, EHCI
* must know about it, too! */
-#define FD_UHCI4 (1 << 11)
-#define FD_UHCI34 ((1 << 10) | FD_UHCI4)
-#define FD_UHCI234 ((1 << 9) | FD_UHCI3)
-#define FD_UHCI1234 ((1 << 8) | FD_UHCI2)
+#define ICH_DISABLE_UHCI(x) (1 << (8 + (x)))
#define FD_INTLAN (1 << 7)
#define FD_ACMOD (1 << 6)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 14:47:47 +0000