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-rw-r--r--src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h4
-rw-r--r--src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c18
-rw-r--r--src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c1
-rw-r--r--src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h1
-rw-r--r--src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c8
-rw-r--r--src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c8
-rw-r--r--src/vendorcode/amd/agesa/Proc/Mem/mm.h6
-rw-r--r--src/vendorcode/amd/agesa/Proc/Mem/mn.h3
-rw-r--r--src/vendorcode/amd/agesa/Proc/Mem/mt.h4
-rw-r--r--src/vendorcode/amd/agesa/Proc/Mem/mu.h1
10 files changed, 29 insertions, 25 deletions
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h
index 7939f1c38b..eedfc0b7c9 100644
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h
+++ b/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h
@@ -151,14 +151,14 @@ GetCurrentNodeNum (
*
*/
UINT32
-GetPlatformNumberOfSockets ();
+GetPlatformNumberOfSockets (VOID);
/**
* Get the number of Modules to check presence in each Processor.
*
*/
UINT32
-GetPlatformNumberOfModules ();
+GetPlatformNumberOfModules (VOID);
BOOLEAN
IsProcessorPresent (
diff --git a/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c
index c0d28a1b6d..90e2918d2d 100644
--- a/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c
+++ b/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c
@@ -70,7 +70,7 @@ RDATA_GROUP (G1_PEICC)
* @retval TRUE Default case, no special action
*/
BOOLEAN
-CommonReturnTrue ()
+CommonReturnTrue (VOID)
{
return TRUE;
}
@@ -83,7 +83,7 @@ CommonReturnTrue ()
* @retval FALSE Default case, no special action
*/
BOOLEAN
-CommonReturnFalse ()
+CommonReturnFalse (VOID)
{
return FALSE;
}
@@ -96,7 +96,7 @@ CommonReturnFalse ()
* @retval zero None, or only case zero.
*/
UINT8
-CommonReturnZero8 ()
+CommonReturnZero8 (VOID)
{
return 0;
}
@@ -109,7 +109,7 @@ CommonReturnZero8 ()
* @retval zero None, or only case zero.
*/
UINT32
-CommonReturnZero32 ()
+CommonReturnZero32 (VOID)
{
return 0;
}
@@ -122,7 +122,7 @@ CommonReturnZero32 ()
* @retval zero None, or only case zero.
*/
UINT64
-CommonReturnZero64 ()
+CommonReturnZero64 (VOID)
{
return 0;
}
@@ -134,7 +134,7 @@ CommonReturnZero64 ()
* @retval NULL pointer to nothing
*/
VOID *
-CommonReturnNULL ()
+CommonReturnNULL (VOID)
{
return NULL;
}
@@ -146,7 +146,7 @@ CommonReturnNULL ()
* @retval AGESA_SUCCESS Success.
*/
AGESA_STATUS
-CommonReturnAgesaSuccess ()
+CommonReturnAgesaSuccess (VOID)
{
return AGESA_SUCCESS;
}
@@ -158,7 +158,7 @@ CommonReturnAgesaSuccess ()
*
*/
VOID
-CommonVoid ()
+CommonVoid (VOID)
{
}
@@ -168,7 +168,7 @@ CommonVoid ()
*
*/
VOID
-CommonAssert ()
+CommonAssert (VOID)
{
ASSERT (FALSE);
}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c
index efd1660e60..e6c7265ea2 100644
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c
+++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c
@@ -115,6 +115,7 @@ NbFmClumpUnitID (
FUSE_TABLE*
NbFmGetFuseTranslationTable (
+ VOID
)
{
return &FuseTable;
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h
index 9442277453..808658c3cf 100644
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h
+++ b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h
@@ -86,6 +86,7 @@ NbFmClumpUnitID (
FUSE_TABLE*
NbFmGetFuseTranslationTable (
+ VOID
);
VOID
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c
index 0214b8deb9..0d80a4ec4d 100644
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c
+++ b/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c
@@ -89,7 +89,7 @@ RDATA_GROUP (G1_PEICC)
*/
VOID
-memDefRet ()
+memDefRet (VOID)
{
}
@@ -100,7 +100,7 @@ memDefRet ()
*
*/
BOOLEAN
-memDefTrue ()
+memDefTrue (VOID)
{
return TRUE;
}
@@ -112,7 +112,7 @@ memDefTrue ()
*
*/
BOOLEAN
-memDefFalse ()
+memDefFalse (VOID)
{
return FALSE;
}
@@ -137,7 +137,7 @@ MemMFlowDef (
*
*/
AGESA_STATUS
-memDefRetSuccess ()
+memDefRetSuccess (VOID)
{
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c
index 29ba56e07a..ced3d938da 100644
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c
+++ b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c
@@ -150,11 +150,11 @@ MemTSkipChipSelPass2Byte (
UINT8
STATIC
-MemTMaxByteLanesByte ();
+MemTMaxByteLanesByte (VOID);
UINT8
STATIC
-MemTDlyTableWidthByte ();
+MemTDlyTableWidthByte (VOID);
VOID
STATIC
@@ -689,7 +689,7 @@ MemTSkipChipSelPass2Byte (
UINT8
STATIC
-MemTMaxByteLanesByte ()
+MemTMaxByteLanesByte (VOID)
{
return MAX_BYTELANES;
}
@@ -704,7 +704,7 @@ MemTMaxByteLanesByte ()
UINT8
STATIC
-MemTDlyTableWidthByte ()
+MemTDlyTableWidthByte (VOID)
{
return MAX_DELAYS;
}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/Proc/Mem/mm.h
index c9e6800513..6497ea33cc 100644
--- a/src/vendorcode/amd/agesa/Proc/Mem/mm.h
+++ b/src/vendorcode/amd/agesa/Proc/Mem/mm.h
@@ -984,10 +984,10 @@ AmdMemInitDataStructDefRecovery (
);
VOID
-MemRecDefRet ();
+MemRecDefRet (VOID);
BOOLEAN
-MemRecDefTrue ();
+MemRecDefTrue (VOID);
VOID
SetMemRecError (
@@ -996,7 +996,7 @@ SetMemRecError (
);
AGESA_STATUS
-memDefRetSuccess ();
+memDefRetSuccess (VOID);
#endif /* _MM_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/Proc/Mem/mn.h
index 9afb81d251..8a06566f18 100644
--- a/src/vendorcode/amd/agesa/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/Proc/Mem/mn.h
@@ -548,7 +548,7 @@ typedef struct _MEM_NB_BLOCK {
VOID (*Feature) (struct _MEM_NB_BLOCK *NBPtr); ///< Feature support.
UINT8 (*GetSocketRelativeChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Dct, UINT8 Channel); ///< Get channel number relative to a socket.
VOID (*SetDramOdtRec) (struct _MEM_NB_BLOCK *NBPtr, ODT_MODE OdtMode, UINT8 ChipSelect, UINT8 TargetCS); ///< Set Dram ODT.
- UINT32 (*GetSysAddrRec) (); ///< Get system address for training.
+ UINT32 (*GetSysAddrRec) (VOID); ///< Get system address for training.
VOID (*SwitchNodeRec) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< Switch to current node.
VOID (*TechBlockSwitch) (struct _MEM_NB_BLOCK *NBPtr); ///< Selects appropriate Tech functions for the NB.
VOID (*SetEccSymbolSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Set Ecc Symbol Size.
@@ -979,6 +979,7 @@ MemRecNCPUMemRecTypingNb (
UINT32
MemRecNGetMCTSysAddrNb (
+ VOID
);
UINT32
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mt.h b/src/vendorcode/amd/agesa/Proc/Mem/mt.h
index d0a3e08da7..ad4d112160 100644
--- a/src/vendorcode/amd/agesa/Proc/Mem/mt.h
+++ b/src/vendorcode/amd/agesa/Proc/Mem/mt.h
@@ -206,11 +206,11 @@ typedef struct _MEM_TECH_BLOCK {
VOID (*SkipChipSelPass1) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
VOID (*SkipChipSelPass2) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
UINT16 (*CompareTestPatternFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< compare training pattern with filter.
- UINT8 (*MaxByteLanes) (); ///< return maximum number of bytelanes.
+ UINT8 (*MaxByteLanes) (VOID); ///< return maximum number of bytelanes.
VOID (*SetDQSDelayCSR) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 Dly); ///< Set CSR.
VOID (*DQSWindowSave) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 DlyMin, UINT8 DlyMax); ///< programs the trained DQS delay for the specified byte lane and stores its DQS window for reference.
BOOLEAN (*FindMaxDlyForMaxRdLat) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< Find maximum receiver enable delay value.
- UINT8 (*DlyTableWidth) (); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes.
+ UINT8 (*DlyTableWidth) (VOID); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes.
UINT16 (*Compare1ClPatternOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT8 Side, UINT8 Receiver, BOOLEAN Side1En); ///< Compare training pattern of 1 cache line.
VOID (*LoadRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value.
VOID (*SetRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value.
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/Proc/Mem/mu.h
index 9627bbaa5c..2a9067dd41 100644
--- a/src/vendorcode/amd/agesa/Proc/Mem/mu.h
+++ b/src/vendorcode/amd/agesa/Proc/Mem/mu.h
@@ -230,6 +230,7 @@ GetVarMtrrHiMsk (
VOID
MemUMFenceInstr (
+ VOID
);
#endif /* _MU_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 20:30:04 +0000