diff options
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/gpio.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 3989ec4e0d..ad934c3e0c 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -56,8 +56,8 @@ chip soc/intel/skylake register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataMode" = "1" - register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index 330ba4eee2..dfd206dd26 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -179,7 +179,7 @@ static const struct pad_config gpio_table[] = { /* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, NF1), /* DB_PCIE_SATA#_DET */ /* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* DEVSLP0_MB */ +/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */ /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* TP328 */ /* CPU_GP1 */ PAD_CFG_NC(GPP_E7), |