diff options
| -rw-r--r-- | src/device/pci_device.c | 67 | ||||
| -rw-r--r-- | src/device/pci_early.c | 48 | ||||
| -rw-r--r-- | src/device/pci_ops.c | 71 | ||||
| -rw-r--r-- | src/drivers/usb/pci_ehci.c | 4 | ||||
| -rw-r--r-- | src/include/device/pci.h | 10 | ||||
| -rw-r--r-- | src/include/device/pci_ops.h | 17 | ||||
| -rw-r--r-- | src/soc/cavium/common/ecam.c | 10 |
7 files changed, 94 insertions, 133 deletions
diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 31c35dc02e..a2af0ec999 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -102,73 +102,6 @@ u32 pci_moving_config32(struct device *dev, unsigned int reg) } /** - * Given a device, a capability type, and a last position, return the next - * matching capability. Always start at the head of the list. - * - * @param dev Pointer to the device structure. - * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. - * @param last Location of the PCI capability register to start from. - * @return The next matching capability. - */ -unsigned pci_find_next_capability(struct device *dev, unsigned cap, - unsigned last) -{ - unsigned pos = 0; - u16 status; - unsigned reps = 48; - - status = pci_read_config16(dev, PCI_STATUS); - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - switch (dev->hdr_type & 0x7f) { - case PCI_HEADER_TYPE_NORMAL: - case PCI_HEADER_TYPE_BRIDGE: - pos = PCI_CAPABILITY_LIST; - break; - case PCI_HEADER_TYPE_CARDBUS: - pos = PCI_CB_CAPABILITY_LIST; - break; - default: - return 0; - } - - pos = pci_read_config8(dev, pos); - while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ - int this_cap; - - pos &= ~3; - this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); - printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n", - this_cap, pos); - if (this_cap == 0xff) - break; - - if (!last && (this_cap == cap)) - return pos; - - if (last == pos) - last = 0; - - pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT); - } - return 0; -} - -/** - * Given a device, and a capability type, return the next matching - * capability. Always start at the head of the list. - * - * @param dev Pointer to the device structure. - * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. - * @return The next matching capability. - */ -unsigned int pci_find_capability(struct device *dev, unsigned int cap) -{ - return pci_find_next_capability(dev, cap, 0); -} - -/** * Given a device and register, read the size of the BAR for that register. * * @param dev Pointer to the device structure. diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 5a1fb22681..7c9ea005c6 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -21,54 +21,6 @@ #include <device/pci_type.h> #include <delay.h> -unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) -{ - unsigned pos = 0; - u16 status; - unsigned reps = 48; - - status = pci_read_config16(dev, PCI_STATUS); - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - u8 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - switch (hdr_type & 0x7f) { - case PCI_HEADER_TYPE_NORMAL: - case PCI_HEADER_TYPE_BRIDGE: - pos = PCI_CAPABILITY_LIST; - break; - case PCI_HEADER_TYPE_CARDBUS: - pos = PCI_CB_CAPABILITY_LIST; - break; - default: - return 0; - } - - pos = pci_read_config8(dev, pos); - while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ - int this_cap; - - pos &= ~3; - this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); - if (this_cap == 0xff) - break; - - if (!last && (this_cap == cap)) - return pos; - - if (last == pos) - last = 0; - - pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT); - } - return 0; -} - -unsigned pci_find_capability(pci_devfn_t dev, unsigned cap) -{ - return pci_find_next_capability(dev, cap, 0); -} - static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) { u16 reg16; diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 34f9d1e5b5..96133155be 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -11,6 +11,77 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <stdint.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_type.h> u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS; + +/** + * Given a device, a capability type, and a last position, return the next + * matching capability. Always start at the head of the list. + * + * @param dev Pointer to the device structure. + * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. + * @param last Location of the PCI capability register to start from. + * @return The next matching capability. + */ +u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last) +{ + u16 pos = 0; + u16 status; + int reps = 48; + + status = pci_s_read_config16(dev, PCI_STATUS); + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + u8 hdr_type = pci_s_read_config8(dev, PCI_HEADER_TYPE); + switch (hdr_type & 0x7f) { + case PCI_HEADER_TYPE_NORMAL: + case PCI_HEADER_TYPE_BRIDGE: + pos = PCI_CAPABILITY_LIST; + break; + case PCI_HEADER_TYPE_CARDBUS: + pos = PCI_CB_CAPABILITY_LIST; + break; + default: + return 0; + } + + pos = pci_s_read_config8(dev, pos); + while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ + int this_cap; + + pos &= ~3; + this_cap = pci_s_read_config8(dev, pos + PCI_CAP_LIST_ID); + if (this_cap == 0xff) + break; + + if (!last && (this_cap == cap)) + return pos; + + if (last == pos) + last = 0; + + pos = pci_s_read_config8(dev, pos + PCI_CAP_LIST_NEXT); + } + return 0; +} + +/** + * Given a device, and a capability type, return the next matching + * capability. Always start at the head of the list. + * + * @param dev Pointer to the device structure. + * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. + * @return The next matching capability. + */ +u16 pci_s_find_capability(pci_devfn_t dev, u16 cap) +{ + return pci_s_find_next_capability(dev, cap, 0); +} diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 5621b37da9..34684cb09a 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -49,7 +49,7 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) if (class != PCI_EHCI_CLASSCODE) return -1; - u8 pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); + u8 pm_cap = pci_s_find_capability(dbg_dev, PCI_CAP_ID_PM); if (pm_cap) { u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL); /* Set to D0 and disable PM events. */ @@ -58,7 +58,7 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); } - u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); + u8 pos = pci_s_find_capability(dbg_dev, PCI_CAP_ID_EHCI_DEBUG); if (!pos) return -1; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f1de7bffa2..5f72b55cff 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -125,16 +125,6 @@ static inline const struct pci_operations *ops_pci(struct device *dev) pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev); pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus); -#ifdef __SIMPLE_DEVICE__ -unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned int cap, - unsigned int last); -unsigned int pci_find_capability(pci_devfn_t dev, unsigned int cap); -#else /* !__SIMPLE_DEVICE__ */ -unsigned int pci_find_next_capability(struct device *dev, unsigned int cap, - unsigned int last); -unsigned int pci_find_capability(struct device *dev, unsigned int cap); -#endif /* __SIMPLE_DEVICE__ */ - void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 454795f519..9a9c575e3c 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -175,4 +175,21 @@ void pci_update_config32(const struct device *dev, u16 reg, u32 mask, u32 or) pci_write_config32(dev, reg, reg32); } +u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last); +u16 pci_s_find_capability(pci_devfn_t dev, u16 cap); + +#ifndef __SIMPLE_DEVICE__ +static __always_inline +u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last) +{ + return pci_s_find_next_capability(PCI_BDF(dev), cap, last); +} + +static __always_inline +u16 pci_find_capability(const struct device *dev, u16 cap) +{ + return pci_s_find_capability(PCI_BDF(dev), cap); +} +#endif + #endif /* PCI_OPS_H */ diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index ae2a91fe0d..89c69dbc2e 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -17,6 +17,8 @@ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ +#define __SIMPLE_DEVICE__ + #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/pci.h> @@ -27,15 +29,11 @@ * Get PCI BAR address from cavium specific extended capability. * Use regular BAR if not found in extended capability space. * - * @return The pyhsical address of the BAR, zero on error + * @return The physical address of the BAR, zero on error */ -#ifdef __SIMPLE_DEVICE__ uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar) -#else -uint64_t ecam0_get_bar_val(struct device *dev, u8 bar) -#endif { - size_t cap_offset = pci_find_capability(dev, 0x14); + size_t cap_offset = pci_s_find_capability(dev, 0x14); uint64_t h, l, ret = 0; if (cap_offset) { /* Found EA */ |