diff options
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_init_setting.c | 11 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 30 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/emi.c | 30 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h | 3 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h | 11 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/emi.h | 4 |
6 files changed, 52 insertions, 37 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index cef77a76fc..7c95c21da4 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -979,7 +979,8 @@ static void dramc_setting_DDR3600(void) clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600); } -static void dramc_setting(const struct sdram_params *params, u8 freq_group) +static void dramc_setting(const struct sdram_params *params, u8 freq_group, + const struct dram_impedance *impedance) { u8 chn; @@ -1399,11 +1400,10 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group) default: die("Invalid DDR frequency group %u\n", freq_group); return; - break; } update_initial_settings(freq_group); - dramc_sw_impedance_save_reg(freq_group); + dramc_sw_impedance_save_reg(freq_group, impedance); clrbits_le32(&ch[0].ao.test2_4, 0x1 << 17); clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0); @@ -1729,9 +1729,10 @@ static void ddr_update_ac_timing(u8 freq_group) clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode); } -void dramc_init(const struct sdram_params *params, u8 freq_group) +void dramc_init(const struct sdram_params *params, u8 freq_group, + const struct dram_impedance *impedance) { - dramc_setting(params, freq_group); + dramc_setting(params, freq_group, impedance); dramc_duty_calibration(params, freq_group); dvfs_settings(freq_group); diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 8f9af608fb..5901f42acc 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -20,8 +20,6 @@ #include <soc/dramc_register.h> #include <soc/dramc_pi_api.h> -static u32 impedance[2][4]; - u8 get_freq_fsq(u8 freq) { if (freq == LP4X_DDR1600 || freq == LP4X_DDR2400) @@ -53,7 +51,8 @@ static void dramc_sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage) clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8); } -void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term) +void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, + struct dram_impedance *impedance) { u32 broadcast_bak, impcal_bak, imp_cal_result; u32 DRVP_result = 0xff, ODTN_result = 0xff, DRVN_result = 0x9; @@ -131,26 +130,25 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term) dramc_show("impedance: term=%d, DRVP=%d, DRVN=%d, ODTN=%d\n", term, DRVP_result, DRVN_result, ODTN_result); + u32 *imp = impedance->data[term]; if (term == ODT_OFF) { - impedance[term][0] = DRVP_result; - impedance[term][1] = ODTN_result; - impedance[term][2] = 0; - impedance[term][3] = 15; + imp[0] = DRVP_result; + imp[1] = ODTN_result; + imp[2] = 0; + imp[3] = 15; } else { - impedance[term][0] = (DRVP_result <= 3) ? - (DRVP_result * 3) : DRVP_result; - impedance[term][1] = (DRVN_result <= 3) ? - (DRVN_result * 3) : DRVN_result; - impedance[term][2] = 0; - impedance[term][3] = (ODTN_result <= 3) ? - (ODTN_result * 3) : ODTN_result; + imp[0] = (DRVP_result <= 3) ? (DRVP_result * 3) : DRVP_result; + imp[1] = (DRVN_result <= 3) ? (DRVN_result * 3) : DRVN_result; + imp[2] = 0; + imp[3] = (ODTN_result <= 3) ? (ODTN_result * 3) : ODTN_result; } dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_TRACKING); dramc_set_broadcast(broadcast_bak); } -void dramc_sw_impedance_save_reg(u8 freq_group) +void dramc_sw_impedance_save_reg(u8 freq_group, + const struct dram_impedance *impedance) { u8 ca_term = ODT_OFF, dq_term = ODT_ON; u32 sw_impedance[2][4] = {0}; @@ -160,7 +158,7 @@ void dramc_sw_impedance_save_reg(u8 freq_group) for (u8 term = 0; term < 2; term++) for (u8 i = 0; i < 4; i++) - sw_impedance[term][i] = impedance[term][i]; + sw_impedance[term][i] = impedance->data[term][i]; sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 8cdbabfebb..653253fb7f 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -349,13 +349,16 @@ static void spm_pinmux_setting(void) write32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); } -static void dfs_init_for_calibration(const struct sdram_params *params, u8 freq_group) +static void dfs_init_for_calibration(const struct sdram_params *params, + u8 freq_group, + struct dram_impedance *impedance) { - dramc_init(params, freq_group); + dramc_init(params, freq_group, impedance); dramc_apply_config_before_calibration(freq_group); } -static void init_dram(const struct sdram_params *params, u8 freq_group) +static void init_dram(const struct sdram_params *params, u8 freq_group, + struct dram_impedance *impedance) { global_option_init(params); emi_init(params); @@ -364,10 +367,11 @@ static void init_dram(const struct sdram_params *params, u8 freq_group) dramc_init_pre_settings(); spm_pinmux_setting(); - dramc_sw_impedance_cal(params, ODT_OFF); - dramc_sw_impedance_cal(params, ODT_ON); + dramc_sw_impedance_cal(params, ODT_OFF, impedance); + dramc_sw_impedance_cal(params, ODT_ON, impedance); - dfs_init_for_calibration(params, freq_group); + dramc_init(params, freq_group, impedance); + dramc_apply_config_before_calibration(freq_group); emi_init2(params); } @@ -487,6 +491,7 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle) } static int run_calib(const struct dramc_param *dparam, + struct dram_impedance *impedance, const int shuffle, bool *first_run) { const u8 *freq_tbl; @@ -505,9 +510,9 @@ static int run_calib(const struct dramc_param *dparam, freq_group, *first_run); if (*first_run) - init_dram(params, freq_group); + init_dram(params, freq_group, impedance); else - dfs_init_for_calibration(params, freq_group); + dfs_init_for_calibration(params, freq_group, impedance); *first_run = false; dramc_show("Start K (current clock: %u\n", params->frequency); @@ -528,17 +533,20 @@ static void after_calib(void) int mt_set_emi(const struct dramc_param *dparam) { + struct dram_impedance impedance; bool first_run = true; set_vdram1_vddq_voltage(); if (CONFIG(MT8183_DRAM_DVFS)) { - if (run_calib(dparam, DRAM_DFS_SHUFFLE_3, &first_run) != 0) + if (run_calib(dparam, &impedance, DRAM_DFS_SHUFFLE_3, + &first_run) != 0) return -1; - if (run_calib(dparam, DRAM_DFS_SHUFFLE_2, &first_run) != 0) + if (run_calib(dparam, &impedance, DRAM_DFS_SHUFFLE_2, + &first_run) != 0) return -1; } - if (run_calib(dparam, DRAM_DFS_SHUFFLE_1, &first_run) != 0) + if (run_calib(dparam, &impedance, DRAM_DFS_SHUFFLE_1, &first_run) != 0) return -1; after_calib(); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index ef6eaf162c..5ea9a52423 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -37,7 +37,8 @@ enum { enum dram_odt_type { ODT_OFF = 0, - ODT_ON + ODT_ON, + ODT_MAX }; enum { diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index afd6718424..65ec075f71 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -105,13 +105,16 @@ void dramc_runtime_config(void); void dramc_set_broadcast(u32 onoff); u32 dramc_get_broadcast(void); u8 get_freq_fsq(u8 freq_group); -void dramc_init(const struct sdram_params *params, u8 freq_group); -void dramc_sw_impedance_save_reg(u8 freq_group); -void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option); +void dramc_init(const struct sdram_params *params, u8 freq_group, + const struct dram_impedance *impedance); +void dramc_sw_impedance_save_reg(u8 freq_group, + const struct dram_impedance *impedance); +void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option, + struct dram_impedance *impedance); void dramc_apply_config_before_calibration(u8 freq_group); void dramc_apply_config_after_calibration(void); int dramc_calibrate_all_channels(const struct sdram_params *pams, - u8 freq_group); + u8 freq_group); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 1a364fb7a6..1b894803bd 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -82,6 +82,10 @@ enum { LP4X_DDRFREQ_MAX, }; +struct dram_impedance { + u32 data[ODT_MAX][4]; +}; + extern const u8 phy_mapping[CHANNEL_MAX][16]; int complex_mem_test(u8 *start, unsigned int len); |