summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/mainboard/asrock/b85m_pro4/romstage.c1
-rw-r--r--src/mainboard/asrock/h81m-hds/romstage.c1
-rw-r--r--src/mainboard/google/beltino/romstage.c1
-rw-r--r--src/mainboard/google/slippy/romstage.c1
-rw-r--r--src/mainboard/intel/baskingridge/romstage.c1
-rw-r--r--src/mainboard/lenovo/t440p/romstage.c1
-rw-r--r--src/mainboard/supermicro/x10slm-f/romstage.c1
-rw-r--r--src/northbridge/intel/haswell/romstage.c1
8 files changed, 1 insertions, 7 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index a2b8607fdc..f625824a8c 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -18,7 +18,6 @@ void mainboard_config_rcba(void)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->system_type = 1; /* Desktop/Server */
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[1] = 0xa2;
pei_data->spd_addresses[2] = 0xa4;
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index 761e9d838a..cfefdda6de 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -18,7 +18,6 @@ void mainboard_config_rcba(void)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->system_type = 1; /* Desktop/Server */
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0;
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 8b3ace2eea..839cd6c743 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -41,7 +41,6 @@ void mainboard_config_rcba(void)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->system_type = 5; /* ULT */
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0;
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index bed81c00e6..e5719448e4 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -42,7 +42,6 @@ void mainboard_config_rcba(void)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->system_type = 5; /* ULT */
pei_data->spd_addresses[0] = 0xff;
pei_data->spd_addresses[2] = 0xff;
pei_data->ec_present = 1;
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 6b7026a465..73fc54ecad 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -42,7 +42,6 @@ void mainboard_config_rcba(void)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[1] = 0xa2;
pei_data->spd_addresses[2] = 0xa4;
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index 5a5f2dec7f..36787603bf 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -42,7 +42,6 @@ void mb_late_romstage_setup(void)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->system_type = 0; /* Mobile */
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa2;
pei_data->ec_present = 1;
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index ddef657d41..26f820a5b5 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -18,7 +18,6 @@ void mainboard_config_rcba(void)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->system_type = 1; /* Desktop/Server */
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[1] = 0xa2;
pei_data->spd_addresses[2] = 0xa4;
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 42a2a56c66..40b7b879d1 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -51,6 +51,7 @@ void mainboard_romstage_entry(void)
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
+ .system_type = get_pch_platform_type(),
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
.max_ddr3_freq = 1600,