diff options
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent.c | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 195a8e7a5c..39ac53f13c 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -158,8 +158,7 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values) * These are the host memory ranges that should be added: * - 0 -> 0xa0000: cacheable * - 0xc0000 -> top_of_ram : cacheable - * - top_of_ram -> BGSM: cacheable with standard MTRRs and reserved - * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved + * - top_of_ram -> TOLUD: not cacheable with standard MTRRs and reserved * - 4GiB -> TOUUD: cacheable * * The default SMRAM space is reserved so that the range doesn't @@ -173,9 +172,10 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values) * is not omitted the mtrr code will setup the area as cacheable * causing VGA access to not work. * - * The TSEG region is mapped as cacheable so that one can perform - * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes - * precedence over the existing MTRRs covering this region. + * Don't need to mark the entire top_of_ram till TOLUD range (used + * for stolen memory like GFX and ME, PTT, DPR, PRMRR, TSEG etc) as + * cacheable for OS usage as coreboot already done with mpinit w/ smm + * relocation early. * * It should be noted that cacheable entry types need to be added in * order. The reason is that the current MTRR code assumes this and @@ -206,13 +206,8 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count) sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> BGSM */ + /* top_of_ram -> TOLUD */ base_k = top_of_ram; - size_k = sa_map_values[SA_BGSM_REG] - base_k; - reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); - - /* BGSM -> TOLUD */ - base_k = sa_map_values[SA_BGSM_REG]; size_k = sa_map_values[SA_TOLUD_REG] - base_k; mmio_resource(dev, index++, base_k / KiB, size_k / KiB); |