diff options
108 files changed, 148 insertions, 242 deletions
diff --git a/src/arch/i386/include/arch/cpu.h b/src/arch/i386/include/arch/cpu.h index f49b7cb50a..d43c847cef 100644 --- a/src/arch/i386/include/arch/cpu.h +++ b/src/arch/i386/include/arch/cpu.h @@ -104,7 +104,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff -#if !defined( __ROMCC__ ) && defined( __GNUC__) +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) && defined( __GNUC__) #include <device/device.h> diff --git a/src/arch/i386/include/arch/hlt.h b/src/arch/i386/include/arch/hlt.h index 3b2acf1eef..931e933fc7 100644 --- a/src/arch/i386/include/arch/hlt.h +++ b/src/arch/i386/include/arch/hlt.h @@ -1,7 +1,7 @@ #ifndef ARCH_HLT_H #define ARCH_HLT_H -#if defined( __ROMCC__) && !defined(__GNUC__) +#if defined( __ROMCC__) && !defined(__PRE_RAM__) && !defined(__GNUC__) static void hlt(void) { __builtin_hlt(); diff --git a/src/arch/i386/include/arch/io.h b/src/arch/i386/include/arch/io.h index 07d091328a..59af68c203 100644 --- a/src/arch/i386/include/arch/io.h +++ b/src/arch/i386/include/arch/io.h @@ -9,7 +9,7 @@ * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" * versions of the single-IO instructions (inb_p/inw_p/..). */ -#if defined( __ROMCC__ ) && !defined (__GNUC__) +#if defined( __ROMCC__ ) && !defined (__GNUC__) static inline void outb(uint8_t value, uint16_t port) { __builtin_outb(value, port); diff --git a/src/arch/i386/lib/console_print.c b/src/arch/i386/lib/console_print.c index ed807e6064..661dc41dcb 100644 --- a/src/arch/i386/lib/console_print.c +++ b/src/arch/i386/lib/console_print.c @@ -66,7 +66,7 @@ static void __console_tx_string(int loglevel, const char *str) * set in some auto.c files to trigger the simple device_t version to be used. * So __GNUCC__ does the right thing here. */ -#if defined (__GNUCC__) +#if defined (__ROMCC__) #define STATIC #else #define STATIC static diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 67beb94dd5..33355cd558 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -2,7 +2,7 @@ #include <arch/cpu.h> #include <cpu/amd/dualcore.h> -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #include <cpu/amd/model_fxx_msr.h> #endif diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 82bb8beda5..1649b8222b 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #include <stdint.h> #include <console/console.h> diff --git a/src/cpu/amd/model_10xxx/apic_timer.c b/src/cpu/amd/model_10xxx/apic_timer.c index d1c0538c1f..d961da795b 100644 --- a/src/cpu/amd/model_10xxx/apic_timer.c +++ b/src/cpu/amd/model_10xxx/apic_timer.c @@ -23,8 +23,8 @@ #include <cpu/x86/lapic.h> /* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (ROMCC). Don't use init_timer() and udelay is redirected - * to udelay_tsc(). + * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is + * redirected to udelay_tsc(). */ diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index ff38c65377..a24b83d42e 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -18,7 +18,7 @@ */ -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -29,7 +29,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ /* From the Revision Guide : * Equivalent Processor Table for AMD Family 10h Processors diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index c4eab24a80..52f5e63f79 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -20,7 +20,7 @@ #include <arch/cpu.h> #include <cpu/amd/quadcore.h> -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #include <cpu/amd/model_10xxx_msr.h> #endif diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 3d1d9d2664..fa94b88113 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -22,7 +22,7 @@ #include <arch/asm.h> // Make sure no stage 2 code is included: -#define __ROMCC__ +#define __PRE_RAM__ // FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? diff --git a/src/drivers/pci/Makefile.inc b/src/drivers/pci/Makefile.inc deleted file mode 100644 index 09ac260c9c..0000000000 --- a/src/drivers/pci/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += onboard diff --git a/src/drivers/pci/onboard/Config.lb b/src/drivers/pci/onboard/Config.lb deleted file mode 100644 index d249df4658..0000000000 --- a/src/drivers/pci/onboard/Config.lb +++ /dev/null @@ -1,4 +0,0 @@ -config chip.h - -object onboard.o - diff --git a/src/drivers/pci/onboard/Makefile.inc b/src/drivers/pci/onboard/Makefile.inc deleted file mode 100644 index 5a16314cce..0000000000 --- a/src/drivers/pci/onboard/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -obj-y += onboard.o diff --git a/src/drivers/pci/onboard/chip.h b/src/drivers/pci/onboard/chip.h deleted file mode 100644 index f06f53ec7a..0000000000 --- a/src/drivers/pci/onboard/chip.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef PCI_ONBOARD_H -#define PCI_ONBOARD_H - -struct drivers_pci_onboard_config -{ - unsigned long rom_address; -}; -struct chip_operations; -extern struct chip_operations drivers_pci_onboard_ops; - -#endif diff --git a/src/drivers/pci/onboard/onboard.c b/src/drivers/pci/onboard/onboard.c deleted file mode 100644 index 58e6816f23..0000000000 --- a/src/drivers/pci/onboard/onboard.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2004 Tyan Computer - * by yhlu@tyan.com - */ - -#include <console/console.h> - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "chip.h" - -/* - * How to use the onboard device driver for option rom execution: - * - * 1. You need to add the driver to your mainboard Config.lb: - * - * chip drivers/pci/onboard - * device pci x.0 on end - * register "rom_address" = "0xfff80000" - * end - * 2. Reduce the size of your normal (or fallback) image, by adding the - * following lines to your target Config.lb, after romimage "normal" - * # 48K for SCSI FW or ATI ROM - * option CONFIG_ROM_SIZE = 512*1024-48*1024 - * 3. Create your vgabios.bin, for example using awardeco and put it in the - * directory of your target Config.lb. You can also read an option rom from - * a running system, but this is unreliable, as some option roms are changed - * during execution: - * # dd if=/dev/mem of=atix.rom skip=1536 count=96 - * 4. After you built coreboot.rom, attach the option rom to your coreboot - * image: - * # cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom - * - * Alternatively you can use the following script "nsxv" to build your image - * Usage: - * # ./nsxv s2850 - * - * #!/bin/bash - * MBVENDOR=tyan - * MBMODEL=$1 - * LBROOT=/home/yhlu/xx/xx - * - * echo $1 - * date - * - * cd "$LBROOT/freebios2/targets" - * rm -rf "$MBVENDOR/$MBMODEL/$MBMODEL" - * ./buildtarget "$MBVENDOR/$MBMODEL" &> "$LBROOT/x_b.txt" - * cd "$MBVENDOR/$MBMODEL/$MBMODEL" - * #make clean - * eval make &> "$LBROOT/x_m.txt" - * if [ $? -eq 0 ]; then - * echo "ok." - * else - * echo "FAILED! Log excerpt:" - * tail -n 15 "$LBROOT/x_m.txt" - * exit - * fi - * cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom" - * cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/ - * - * date - * - */ - -static void onboard_enable(device_t dev) -{ - struct drivers_pci_onboard_config *conf; - conf = dev->chip_info; - dev->rom_address = conf->rom_address; -} - -struct chip_operations drivers_pci_onboard_ops = { - CHIP_NAME("Onboard PCI") - .enable_dev = onboard_enable, -}; diff --git a/src/include/assert.h b/src/include/assert.h index d34d557e06..4103291461 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -24,7 +24,7 @@ // ROMCC doesn't support __FILE__ or __LINE__ :^{ #if CONFIG_DEBUG -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); } #else #define ASSERT(x) { \ @@ -39,7 +39,7 @@ #define ASSERT(x) { } #endif -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #define BUG() { die("BUG encountered: system halted\r\n"); } #else #define BUG() { \ diff --git a/src/include/cpu/amd/dualcore.h b/src/include/cpu/amd/dualcore.h index fb53c92909..1d33840668 100644 --- a/src/include/cpu/amd/dualcore.h +++ b/src/include/cpu/amd/dualcore.h @@ -15,7 +15,7 @@ struct node_core_id { struct node_core_id get_node_core_id(unsigned int nb_cfg_54); #endif -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) struct device; unsigned get_apicid_base(unsigned ioapic_num); void amd_sibling_init(struct device *cpu); diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index a3f3033b28..c2d59a62de 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -49,7 +49,7 @@ static inline int is_cpu_e0(void) } -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ static int is_e0_later_in_bsp(int nodeid) { uint32_t val; @@ -96,7 +96,7 @@ static inline int is_cpu_pre_f2(void) return (cpuid_eax(1) & 0xfff0f) < 0x40f02; } -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ //AMD_F0_SUPPORT static int is_cpu_f0_in_bsp(int nodeid) { diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 2b7017d897..d86655dcdd 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -31,7 +31,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) +#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) && !defined(__PRE_RAM__) void amd_setup_mtrrs(void); #endif /* __ROMCC__ */ diff --git a/src/include/cpu/amd/quadcore.h b/src/include/cpu/amd/quadcore.h index 54a1c9be22..f7b2d09a19 100644 --- a/src/include/cpu/amd/quadcore.h +++ b/src/include/cpu/amd/quadcore.h @@ -34,7 +34,7 @@ struct node_core_id { struct node_core_id get_node_core_id(u32 nb_cfg_54); #endif -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) struct device; u32 get_apicid_base(u32 ioapic_num); void amd_sibling_init(struct device *cpu); diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index af7d3d52ef..22bd1e7e47 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -41,7 +41,7 @@ static inline void disable_cache(void) wbinvd(); } -#if !defined( __ROMCC__) && defined (__GNUC__) +#if !defined( __ROMCC__) && !defined(__PRE_RAM__) && defined (__GNUC__) void x86_enable_cache(void); #endif /* !__ROMCC__ */ diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 9f2191940a..2b77177bbf 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -68,7 +68,7 @@ static inline __attribute__((always_inline)) void stop_this_cpu(void) } #endif -#if ! defined (__ROMCC__) +#if ! defined (__ROMCC__) && !defined(__PRE_RAM__) #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr)))) @@ -157,6 +157,6 @@ int start_cpu(struct device *cpu); #endif /* CONFIG_SMP */ -#endif /* !__ROMCC__ */ +#endif /* !__ROMCC__ && !__PRE_RAM__ */ #endif /* CPU_X86_LAPIC_H */ diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index c4bc55a343..69b4d8e78a 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -1,7 +1,7 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H -#if defined( __ROMCC__) && !defined (__GNUC__) +#if defined( __ROMCC__) typedef __builtin_msr_t msr_t; @@ -43,7 +43,7 @@ static inline void wrmsr(unsigned index, msr_t msr) ); } -#endif /* ROMCC__ && !__GNUC__ */ +#endif /* __ROMCC__ */ #endif /* CPU_X86_MSR_H */ diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 704a9d4bb1..2243fe3080 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -32,7 +32,7 @@ #define MTRRfix4K_F8000_MSR 0x26f -#if !defined(__ROMCC__) && !defined (ASSEMBLY) +#if !defined(__ROMCC__) && !defined (ASSEMBLY) && !defined(__PRE_RAM__) #include <device/device.h> diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 455cd239fe..9370adfe00 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -17,7 +17,7 @@ static tsc_t rdtsc(void) return res; } -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined (__PRE_RAM__) static inline unsigned long long rdtscll(void) { unsigned long long val; diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 63a316f186..8742fdfe85 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -11,7 +11,7 @@ #define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b)) -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) void *malloc(size_t size); void free(void *ptr); #endif diff --git a/src/include/string.h b/src/include/string.h index 1b092a6c2a..9e3c08450e 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -8,7 +8,7 @@ void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) int sprintf(char * buf, const char *fmt, ...); #endif @@ -41,7 +41,7 @@ static inline char *strchr(const char *s, int c) return 0; } -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) static inline char *strdup(const char *s) { size_t sz = strlen(s) + 1; diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 83779a7ee8..023ddeaeb2 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -45,7 +45,7 @@ struct cbmem_entry { u64 size; } __attribute__((packed)); -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ struct cbmem_entry *bss_cbmem_toc; #endif @@ -64,7 +64,7 @@ void cbmem_init(u64 baseaddr, u64 size) struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ bss_cbmem_toc = cbmem_toc; #endif @@ -91,7 +91,7 @@ int cbmem_reinit(u64 baseaddr) cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; debug("Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr); -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ bss_cbmem_toc = cbmem_toc; #endif @@ -102,7 +102,7 @@ void *cbmem_add(u32 id, u64 size) { struct cbmem_entry *cbmem_toc; int i; -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); #else cbmem_toc = bss_cbmem_toc; @@ -158,7 +158,7 @@ void *cbmem_find(u32 id) { struct cbmem_entry *cbmem_toc; int i; -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); #else cbmem_toc = bss_cbmem_toc; @@ -175,7 +175,7 @@ void *cbmem_find(u32 id) return (void *)NULL; } -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif @@ -199,12 +199,12 @@ void cbmem_initialize(void) cbmem_arch_init(); } -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ void cbmem_list(void) { struct cbmem_entry *cbmem_toc; int i; -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); #else cbmem_toc = bss_cbmem_toc; diff --git a/src/lib/usbdebug_direct.c b/src/lib/usbdebug_direct.c index 48875dc610..1fd1113867 100644 --- a/src/lib/usbdebug_direct.c +++ b/src/lib/usbdebug_direct.c @@ -19,7 +19,7 @@ /* * 2006.12.10 yhlu moved it to corbeoot and use struct instead */ -#ifndef __ROMCC__ +#if !defined(__ROMCC__) #include <console/console.h> #else #if CONFIG_USE_PRINTK_IN_CAR==0 diff --git a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c index b058b445f3..c83759bbad 100644 --- a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c +++ b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c @@ -18,7 +18,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 diff --git a/src/mainboard/amd/pistachio/cache_as_ram_auto.c b/src/mainboard/amd/pistachio/cache_as_ram_auto.c index 4615901fe7..2e5c4a0812 100644 --- a/src/mainboard/amd/pistachio/cache_as_ram_auto.c +++ b/src/mainboard/amd/pistachio/cache_as_ram_auto.c @@ -18,7 +18,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 diff --git a/src/mainboard/amd/serengeti_cheetah/apc_auto.c b/src/mainboard/amd/serengeti_cheetah/apc_auto.c index a855c2fd39..6abebffe13 100644 --- a/src/mainboard/amd/serengeti_cheetah/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah/apc_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c index a3e2b164a5..2626f8012a 100644 --- a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c index ea7e2a6b29..a62811a228 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c @@ -18,7 +18,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c index abb28917c1..0b136ec910 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c @@ -19,7 +19,7 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define SYSTEM_TYPE 0 /* SERVER */ //#define SYSTEM_TYPE 1 /* DESKTOP */ diff --git a/src/mainboard/arima/hdama/cache_as_ram_auto.c b/src/mainboard/arima/hdama/cache_as_ram_auto.c index 4bbd4285e7..19c4c6bc3f 100644 --- a/src/mainboard/arima/hdama/cache_as_ram_auto.c +++ b/src/mainboard/arima/hdama/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c index 021a226427..8e0ba2925e 100644 --- a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c @@ -22,7 +22,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ /* Used by it8712f_enable_serial(). */ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) diff --git a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c index 6f54ecfcc7..4ec3aee813 100644 --- a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c @@ -23,7 +23,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c b/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c index 5a7f74ba37..13101b0217 100644 --- a/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c +++ b/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c @@ -23,7 +23,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/broadcom/blast/cache_as_ram_auto.c b/src/mainboard/broadcom/blast/cache_as_ram_auto.c index 3b94d3fd32..6169841f69 100644 --- a/src/mainboard/broadcom/blast/cache_as_ram_auto.c +++ b/src/mainboard/broadcom/blast/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/dell/s1850/reset.c b/src/mainboard/dell/s1850/reset.c index 28a019a7d9..293ad72663 100644 --- a/src/mainboard/dell/s1850/reset.c +++ b/src/mainboard/dell/s1850/reset.c @@ -2,7 +2,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/pci.h> #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c index 5a94cf740f..452084f7c4 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c @@ -22,7 +22,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c index 056cd08331..69e06bc2e5 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c @@ -22,7 +22,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/gigabyte/m57sli/apc_auto.c b/src/mainboard/gigabyte/m57sli/apc_auto.c index 50ad68eed3..007dfa9a95 100644 --- a/src/mainboard/gigabyte/m57sli/apc_auto.c +++ b/src/mainboard/gigabyte/m57sli/apc_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c index 26e5ee985e..ecc7827428 100644 --- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c +++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c b/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c index 0f54f46af2..525cb3e102 100644 --- a/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c +++ b/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c @@ -26,7 +26,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/ibm/e325/cache_as_ram_auto.c b/src/mainboard/ibm/e325/cache_as_ram_auto.c index 1021a6061e..6621bf1272 100644 --- a/src/mainboard/ibm/e325/cache_as_ram_auto.c +++ b/src/mainboard/ibm/e325/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/ibm/e326/cache_as_ram_auto.c b/src/mainboard/ibm/e326/cache_as_ram_auto.c index c6794a9902..0ec2c52f48 100644 --- a/src/mainboard/ibm/e326/cache_as_ram_auto.c +++ b/src/mainboard/ibm/e326/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/intel/d945gclf/auto.c b/src/mainboard/intel/d945gclf/auto.c index 890caa00fc..e0c4c52348 100644 --- a/src/mainboard/intel/d945gclf/auto.c +++ b/src/mainboard/intel/d945gclf/auto.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -// __ROMCC__ means: use "unsigned" for device, not a struct. -#define __ROMCC__ +// __PRE_RAM__ means: use "unsigned" for device, not a struct. +#define __PRE_RAM__ #include <stdint.h> #include <string.h> @@ -220,10 +220,10 @@ static void early_ich7_init(void) #include <cbmem.h> // Now, this needs to be included because it relies on the symbol -// __ROMCC_ being set during CAR stage (in order to compile the +// __PRE_RAM__ being set during CAR stage (in order to compile the // BSS free versions of the functions). Either rewrite the code // to be always BSS free, or invent a flag that's better suited than -// __ROMCC__ to determine whether we're in ram init stage (stage 1) +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) // #include "lib/cbmem.c" diff --git a/src/mainboard/intel/eagleheights/auto.c b/src/mainboard/intel/eagleheights/auto.c index 2dce5bb6c3..47043a9067 100644 --- a/src/mainboard/intel/eagleheights/auto.c +++ b/src/mainboard/intel/eagleheights/auto.c @@ -20,7 +20,7 @@ * MA 02110-1301 USA */ -#define __ROMCC__ +#define __PRE_RAM__ #include <delay.h> diff --git a/src/mainboard/intel/eagleheights/reset.c b/src/mainboard/intel/eagleheights/reset.c index d35a6dc629..09308e4678 100644 --- a/src/mainboard/intel/eagleheights/reset.c +++ b/src/mainboard/intel/eagleheights/reset.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/mainboard/intel/jarrell/reset.c b/src/mainboard/intel/jarrell/reset.c index b09b70899d..5364632346 100644 --- a/src/mainboard/intel/jarrell/reset.c +++ b/src/mainboard/intel/jarrell/reset.c @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/mainboard/intel/xe7501devkit/auto.c b/src/mainboard/intel/xe7501devkit/auto.c index 8e2c271f2b..7269fa8d43 100644 --- a/src/mainboard/intel/xe7501devkit/auto.c +++ b/src/mainboard/intel/xe7501devkit/auto.c @@ -1,4 +1,5 @@ #define ASSEMBLY 1 +#define __PRE_RAM__ #include <stdint.h> #include <device/pci_def.h> diff --git a/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c b/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c index 76e56f80a4..cdfdfc09c5 100644 --- a/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c +++ b/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c b/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c index 78b1de980d..271ad6cc54 100644 --- a/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c +++ b/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/iwill/dk8x/cache_as_ram_auto.c b/src/mainboard/iwill/dk8x/cache_as_ram_auto.c index 78b1de980d..271ad6cc54 100644 --- a/src/mainboard/iwill/dk8x/cache_as_ram_auto.c +++ b/src/mainboard/iwill/dk8x/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/kontron/986lcd-m/auto.c b/src/mainboard/kontron/986lcd-m/auto.c index 003fdb393f..f8304111ce 100644 --- a/src/mainboard/kontron/986lcd-m/auto.c +++ b/src/mainboard/kontron/986lcd-m/auto.c @@ -19,8 +19,8 @@ * MA 02110-1301 USA */ -// __ROMCC__ means: use "unsigned" for device, not a struct. -#define __ROMCC__ +// __PRE_RAM__ means: use "unsigned" for device, not a struct. +#define __PRE_RAM__ #include <stdint.h> #include <string.h> @@ -359,10 +359,10 @@ static void early_ich7_init(void) #include <cbmem.h> // Now, this needs to be included because it relies on the symbol -// __ROMCC_ being set during CAR stage (in order to compile the +// __PRE_RAM__ being set during CAR stage (in order to compile the // BSS free versions of the functions). Either rewrite the code // to be always BSS free, or invent a flag that's better suited than -// __ROMCC__ to determine whether we're in ram init stage (stage 1) +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) // #include "lib/cbmem.c" diff --git a/src/mainboard/kontron/kt690/cache_as_ram_auto.c b/src/mainboard/kontron/kt690/cache_as_ram_auto.c index 68447baa97..224f60365d 100644 --- a/src/mainboard/kontron/kt690/cache_as_ram_auto.c +++ b/src/mainboard/kontron/kt690/cache_as_ram_auto.c @@ -19,7 +19,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 diff --git a/src/mainboard/msi/ms7135/cache_as_ram_auto.c b/src/mainboard/msi/ms7135/cache_as_ram_auto.c index 4b5ab60dcc..6616dc1444 100644 --- a/src/mainboard/msi/ms7135/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms7135/cache_as_ram_auto.c @@ -23,7 +23,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1) diff --git a/src/mainboard/msi/ms7260/apc_auto.c b/src/mainboard/msi/ms7260/apc_auto.c index 317f9d26d3..84ba6c1daf 100644 --- a/src/mainboard/msi/ms7260/apc_auto.c +++ b/src/mainboard/msi/ms7260/apc_auto.c @@ -21,7 +21,7 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/msi/ms7260/cache_as_ram_auto.c b/src/mainboard/msi/ms7260/cache_as_ram_auto.c index ed84a426b2..7a8bf13a79 100644 --- a/src/mainboard/msi/ms7260/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms7260/cache_as_ram_auto.c @@ -21,7 +21,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ // #define CACHE_AS_RAM_ADDRESS_DEBUG 1 // #define DEBUG_SMBUS 1 diff --git a/src/mainboard/msi/ms9185/cache_as_ram_auto.c b/src/mainboard/msi/ms9185/cache_as_ram_auto.c index 95704b9791..255815707a 100644 --- a/src/mainboard/msi/ms9185/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms9185/cache_as_ram_auto.c @@ -24,7 +24,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/msi/ms9282/cache_as_ram_auto.c b/src/mainboard/msi/ms9282/cache_as_ram_auto.c index 55f2a33273..11c92b81fa 100644 --- a/src/mainboard/msi/ms9282/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms9282/cache_as_ram_auto.c @@ -23,7 +23,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/newisys/khepri/cache_as_ram_auto.c b/src/mainboard/newisys/khepri/cache_as_ram_auto.c index db76c95d77..efd2ea3a97 100644 --- a/src/mainboard/newisys/khepri/cache_as_ram_auto.c +++ b/src/mainboard/newisys/khepri/cache_as_ram_auto.c @@ -4,7 +4,7 @@ * Additional (C) 2007 coresystems GmbH */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/nvidia/l1_2pvv/apc_auto.c b/src/mainboard/nvidia/l1_2pvv/apc_auto.c index d7c4e2831a..1a9121e40f 100644 --- a/src/mainboard/nvidia/l1_2pvv/apc_auto.c +++ b/src/mainboard/nvidia/l1_2pvv/apc_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c b/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c index 04fa546f6a..ab6941f22d 100644 --- a/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c +++ b/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/sunw/ultra40/cache_as_ram_auto.c b/src/mainboard/sunw/ultra40/cache_as_ram_auto.c index 468e049750..9a3f948036 100644 --- a/src/mainboard/sunw/ultra40/cache_as_ram_auto.c +++ b/src/mainboard/sunw/ultra40/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define K8_ALLOCATE_IO_RANGE 1 diff --git a/src/mainboard/supermicro/h8dme/apc_auto.c b/src/mainboard/supermicro/h8dme/apc_auto.c index b501cfc76e..bb625933e7 100644 --- a/src/mainboard/supermicro/h8dme/apc_auto.c +++ b/src/mainboard/supermicro/h8dme/apc_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c index 151b2d0a4a..72d5809ea4 100644 --- a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c +++ b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c @@ -17,7 +17,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/supermicro/h8dmr/apc_auto.c b/src/mainboard/supermicro/h8dmr/apc_auto.c index b501cfc76e..bb625933e7 100644 --- a/src/mainboard/supermicro/h8dmr/apc_auto.c +++ b/src/mainboard/supermicro/h8dmr/apc_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c index 672f551fa1..9c675274af 100644 --- a/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c +++ b/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c b/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c index f55b80f826..647637d66e 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c +++ b/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c index 02615bba0a..4ebc47f6a0 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c +++ b/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/supermicro/x6dai_g/reset.c b/src/mainboard/supermicro/x6dai_g/reset.c index f57d7a5098..e168e37a2f 100644 --- a/src/mainboard/supermicro/x6dai_g/reset.c +++ b/src/mainboard/supermicro/x6dai_g/reset.c @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/mainboard/supermicro/x6dhe_g/reset.c b/src/mainboard/supermicro/x6dhe_g/reset.c index b09b70899d..5364632346 100644 --- a/src/mainboard/supermicro/x6dhe_g/reset.c +++ b/src/mainboard/supermicro/x6dhe_g/reset.c @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/mainboard/supermicro/x6dhe_g2/reset.c b/src/mainboard/supermicro/x6dhe_g2/reset.c index b09b70899d..5364632346 100644 --- a/src/mainboard/supermicro/x6dhe_g2/reset.c +++ b/src/mainboard/supermicro/x6dhe_g2/reset.c @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/mainboard/supermicro/x6dhr_ig/reset.c b/src/mainboard/supermicro/x6dhr_ig/reset.c index b09b70899d..5364632346 100644 --- a/src/mainboard/supermicro/x6dhr_ig/reset.c +++ b/src/mainboard/supermicro/x6dhr_ig/reset.c @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/mainboard/supermicro/x6dhr_ig2/reset.c b/src/mainboard/supermicro/x6dhr_ig2/reset.c index b09b70899d..5364632346 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/reset.c +++ b/src/mainboard/supermicro/x6dhr_ig2/reset.c @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/mainboard/technexion/tim5690/cache_as_ram_auto.c b/src/mainboard/technexion/tim5690/cache_as_ram_auto.c index ce2d6b3eba..7e4e100d43 100644 --- a/src/mainboard/technexion/tim5690/cache_as_ram_auto.c +++ b/src/mainboard/technexion/tim5690/cache_as_ram_auto.c @@ -18,7 +18,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 diff --git a/src/mainboard/technexion/tim8690/cache_as_ram_auto.c b/src/mainboard/technexion/tim8690/cache_as_ram_auto.c index 26407076bf..ff86ba3713 100644 --- a/src/mainboard/technexion/tim8690/cache_as_ram_auto.c +++ b/src/mainboard/technexion/tim8690/cache_as_ram_auto.c @@ -18,7 +18,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 diff --git a/src/mainboard/tyan/s2735/cache_as_ram_auto.c b/src/mainboard/tyan/s2735/cache_as_ram_auto.c index 8656d3dd5d..99a38a9fb3 100644 --- a/src/mainboard/tyan/s2735/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2735/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/tyan/s2850/cache_as_ram_auto.c b/src/mainboard/tyan/s2850/cache_as_ram_auto.c index 871e2bac6a..352feadf70 100644 --- a/src/mainboard/tyan/s2850/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2850/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/tyan/s2875/cache_as_ram_auto.c b/src/mainboard/tyan/s2875/cache_as_ram_auto.c index 56fbdae186..50b12f1ff6 100644 --- a/src/mainboard/tyan/s2875/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2875/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/tyan/s2880/cache_as_ram_auto.c b/src/mainboard/tyan/s2880/cache_as_ram_auto.c index db520eb360..c97f3b7708 100644 --- a/src/mainboard/tyan/s2880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2880/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/tyan/s2881/cache_as_ram_auto.c b/src/mainboard/tyan/s2881/cache_as_ram_auto.c index 69000f15a3..9d5edcb462 100644 --- a/src/mainboard/tyan/s2881/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2881/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/tyan/s2882/cache_as_ram_auto.c b/src/mainboard/tyan/s2882/cache_as_ram_auto.c index 1fd98ff5bf..cdea6933ed 100644 --- a/src/mainboard/tyan/s2882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2882/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/tyan/s2885/cache_as_ram_auto.c b/src/mainboard/tyan/s2885/cache_as_ram_auto.c index edea2b9de2..d561e033c6 100644 --- a/src/mainboard/tyan/s2885/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2885/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/tyan/s2891/cache_as_ram_auto.c b/src/mainboard/tyan/s2891/cache_as_ram_auto.c index 93b640ac11..9ace5e30ae 100644 --- a/src/mainboard/tyan/s2891/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2891/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/tyan/s2892/cache_as_ram_auto.c b/src/mainboard/tyan/s2892/cache_as_ram_auto.c index ffe11034d5..e94017e532 100644 --- a/src/mainboard/tyan/s2892/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2892/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c index 77bd04d330..78ddd1c6a3 100644 --- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define K8_ALLOCATE_IO_RANGE 1 diff --git a/src/mainboard/tyan/s2895/failover.c b/src/mainboard/tyan/s2895/failover.c index cb70a2e9de..25f488dac4 100644 --- a/src/mainboard/tyan/s2895/failover.c +++ b/src/mainboard/tyan/s2895/failover.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/tyan/s2912/apc_auto.c b/src/mainboard/tyan/s2912/apc_auto.c index 880d06a1cf..3e98a5c979 100644 --- a/src/mainboard/tyan/s2912/apc_auto.c +++ b/src/mainboard/tyan/s2912/apc_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/tyan/s2912/cache_as_ram_auto.c b/src/mainboard/tyan/s2912/cache_as_ram_auto.c index 8fb6473499..ce466306ce 100644 --- a/src/mainboard/tyan/s2912/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2912/cache_as_ram_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/tyan/s2912_fam10/apc_auto.c b/src/mainboard/tyan/s2912_fam10/apc_auto.c index 880d06a1cf..3e98a5c979 100644 --- a/src/mainboard/tyan/s2912_fam10/apc_auto.c +++ b/src/mainboard/tyan/s2912_fam10/apc_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c b/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c index f085a699b5..1216c298b9 100644 --- a/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 diff --git a/src/mainboard/tyan/s4880/cache_as_ram_auto.c b/src/mainboard/tyan/s4880/cache_as_ram_auto.c index 61085a8d57..9f38ec1992 100644 --- a/src/mainboard/tyan/s4880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4880/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/tyan/s4882/cache_as_ram_auto.c b/src/mainboard/tyan/s4882/cache_as_ram_auto.c index 88637b6dd4..1c8d3b42fe 100644 --- a/src/mainboard/tyan/s4882/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4882/cache_as_ram_auto.c @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> diff --git a/src/mainboard/via/epia-m700/cache_as_ram_auto.c b/src/mainboard/via/epia-m700/cache_as_ram_auto.c index 9c6036af8c..45e8118617 100644 --- a/src/mainboard/via/epia-m700/cache_as_ram_auto.c +++ b/src/mainboard/via/epia-m700/cache_as_ram_auto.c @@ -23,7 +23,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 4cca443716..826037194d 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -956,7 +956,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "amdfam10_nums.h" -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #if NODE_NUMS==64 #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else @@ -1086,7 +1086,7 @@ struct sys_info { #if CONFIG_AMDMCT == 0 -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ static void soft_reset(void); #endif static void wait_all_core0_mem_trained(struct sys_info *sysinfo) @@ -1131,7 +1131,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) } for(i=0; i<sysinfo->nodes; i++) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); #else printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); @@ -1148,7 +1148,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) } } if(needs_reset) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem trained failed\n"); soft_reset(); #else diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c index cd958c5216..b52bedad7b 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_conf.c +++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) typedef struct sys_info sys_info_conf_t; #else typedef struct amdfam10_sysconf_t sys_info_conf_t; @@ -32,7 +32,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { device_t dev; struct dram_base_mask_t d; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); #else dev = __f1_dev[0]; @@ -88,7 +88,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) #endif for(i=0;i<nodes;i++) { -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -108,7 +108,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) #endif } -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(nodeid, 1); #else dev = __f1_dev[nodeid]; @@ -122,7 +122,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) static void set_DctSelBaseAddr(u32 i, u32 sel_m) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -139,7 +139,7 @@ static void set_DctSelBaseAddr(u32 i, u32 sel_m) static u32 get_DctSelBaseAddr(u32 i) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -156,7 +156,7 @@ static u32 get_DctSelBaseAddr(u32 i) static void set_DctSelHiEn(u32 i, u32 val) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -172,7 +172,7 @@ static void set_DctSelHiEn(u32 i, u32 val) static u32 get_DctSelHiEn(u32 i) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -187,7 +187,7 @@ static u32 get_DctSelHiEn(u32 i) static void set_DctSelBaseOffset(u32 i, u32 sel_off_m) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -203,7 +203,7 @@ static void set_DctSelBaseOffset(u32 i, u32 sel_off_m) static u32 get_DctSelBaseOffset(u32 i) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -264,7 +264,7 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) d = get_dram_base_mask(i); d.mask += (carry_over>>9); set_dram_base_mask(i,d, nodes); -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -330,7 +330,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, index_max = busn_max>>2; dest_max = busn_max - (index_max<<2); // three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(nodeid, 1); #else dev = __f1_dev[nodeid]; @@ -393,7 +393,7 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #endif tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -433,7 +433,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, if(ht_c_index<4) { #endif for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -480,7 +480,7 @@ static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, } #endif -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { @@ -494,7 +494,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -503,7 +503,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, } tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for(i=0; i<nodes; i++){ - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -546,7 +546,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #endif /* io range allocation */ for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -584,7 +584,7 @@ static void re_set_all_config_map_reg(u32 nodes, u32 segbit, for(ht_c_index=1;ht_c_index<4; ht_c_index++) { u32 i; for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -664,7 +664,7 @@ static void set_BusSegmentEn(u32 node, u32 segbit) u32 dword; device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(node, 0); #else dev = __f0_dev[node]; @@ -677,7 +677,7 @@ static void set_BusSegmentEn(u32 node, u32 segbit) #endif } -#if !defined(__ROMCC__) +#if !defined(__PRE_RAM__) static u32 get_io_addr_index(u32 nodeid, u32 linkn) { u32 index; diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h index 68f9655adc..7010e80bd6 100644 --- a/src/northbridge/amd/amdk8/amdk8_f.h +++ b/src/northbridge/amd/amdk8/amdk8_f.h @@ -518,7 +518,7 @@ struct sys_info { uint32_t sbbusn; } __attribute__((packed)); -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ static void soft_reset(void); #else void hard_reset(void); @@ -562,7 +562,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) } for(i=0; i<sysinfo->nodes; i++) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n"); #else printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); @@ -579,7 +579,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo) } } if(needs_reset) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem trained failed\r\n"); soft_reset(); #else diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h index a98af45410..400aaf308a 100644 --- a/src/northbridge/via/cn700/cn700.h +++ b/src/northbridge/via/cn700/cn700.h @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) static void cn700_noop() { } diff --git a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c b/src/northbridge/via/vx800/examples/cache_as_ram_auto.c index 30204432a3..fa8962b168 100644 --- a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c +++ b/src/northbridge/via/vx800/examples/cache_as_ram_auto.c @@ -19,7 +19,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 diff --git a/src/southbridge/amd/cs5530/cs5530.h b/src/southbridge/amd/cs5530/cs5530.h index 107b6f26e5..283b64de33 100644 --- a/src/southbridge/amd/cs5530/cs5530.h +++ b/src/southbridge/amd/cs5530/cs5530.h @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H #define SOUTHBRIDGE_AMD_CS5530_CS5530_H -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" void cs5530_enable(device_t dev); #endif diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 00c19e04e3..f105571380 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" void i82371eb_enable(device_t dev); void i82371eb_hard_reset(void); diff --git a/src/southbridge/intel/i82801ca/i82801ca.h b/src/southbridge/intel/i82801ca/i82801ca.h index 59056f29df..a761056bff 100644 --- a/src/southbridge/intel/i82801ca/i82801ca.h +++ b/src/southbridge/intel/i82801ca/i82801ca.h @@ -1,7 +1,7 @@ #ifndef I82801CA_H #define I82801CA_H -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" extern void i82801ca_enable(device_t dev); #endif diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 9b54fc6008..5c29c9ea62 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -41,7 +41,7 @@ /* __ROMCC__ is set by auto.c to make sure * none of the stage2 data structures are included. */ -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); #endif diff --git a/src/southbridge/intel/i82801xx/i82801xx.h b/src/southbridge/intel/i82801xx/i82801xx.h index 27ce21c207..d90cc32b37 100644 --- a/src/southbridge/intel/i82801xx/i82801xx.h +++ b/src/southbridge/intel/i82801xx/i82801xx.h @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H #define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" extern void i82801xx_enable(device_t dev); #endif |