diff options
27 files changed, 51 insertions, 160 deletions
diff --git a/src/cpu/amd/microcode/Makefile.inc b/src/cpu/amd/microcode/Makefile.inc index 6631019f38..48f1d0d136 100644 --- a/src/cpu/amd/microcode/Makefile.inc +++ b/src/cpu/amd/microcode/Makefile.inc @@ -1 +1,2 @@ ramstage-y += microcode.c +romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += microcode.c diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 1e94daba08..46d814e0c9 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -17,17 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __ROMCC__ #include <stdint.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/amd/microcode.h> -#endif - -#ifndef __PRE_RAM__ -#include <cpu/cpu.h> -#include <cpu/x86/cache.h> -#endif struct microcode { u32 date_code; diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index 81c565b621..c78f6403d8 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += model_10xxx_init.c -ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c ramstage-y += processor_name.c + +romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index eb047b8db2..3ebd7f2358 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -325,9 +325,8 @@ static u32 init_cpus(u32 cpu_init_detectedx) * This happens after HTinit. * The BSP runs this code in it's own path. */ -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(cpuid_eax(1)); -#endif + cpuSetAMDMSR(); #if CONFIG_SET_FIDVID diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index cc08cdc546..95624e94c6 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -17,17 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#ifndef __PRE_RAM__ +#include <stdint.h> #include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#endif - -#ifndef __ROMCC__ #include <cpu/amd/microcode.h> -#endif static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index f1747d98af..4a53feaa29 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -20,9 +20,6 @@ */ #include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> #include <cpu/amd/microcode.h> static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index b40200bca0..e6d686c36a 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -2,7 +2,12 @@ #define CPU_AMD_MICROCODE_H void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id); -void update_microcode(u32 processor_rev_id); void model_fxx_update_microcode(unsigned cpu_deviceid); + +#if CONFIG_UPDATE_CPU_MICROCODE +void update_microcode(u32 processor_rev_id); +#else +#define update_microcode(x) +#endif #endif /* CPU_AMD_MICROCODE_H */ diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 8e7aa40bb0..30616c58c5 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -65,10 +65,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" @@ -126,9 +123,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 7afec9a9fb..1367f9f61d 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -64,11 +64,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -124,9 +120,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index a9f8b46c85..1075e818fe 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -64,11 +64,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -120,9 +116,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index c5adab3eeb..c4de048e0c 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -85,11 +85,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -228,9 +224,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 0c6126b399..e2d59e692d 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -63,11 +63,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -120,9 +116,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index f19fa8dd8d..72058b92d3 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -63,11 +63,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -121,9 +117,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index f8d668093a..d5a92f3453 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -63,11 +63,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -121,9 +117,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 368b6592f4..c0548ff09a 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -65,10 +65,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" @@ -125,9 +122,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 39c72477d1..81ded79540 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -65,10 +65,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" @@ -126,9 +123,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 056e0df5d1..12c7967b2c 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -59,11 +59,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -116,9 +112,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 056e0df5d1..12c7967b2c 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -59,11 +59,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -116,9 +112,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 431e554877..116475c1a2 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -63,11 +63,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -119,9 +115,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 11a8d08d0f..d5d43710f1 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -79,11 +79,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/pci.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -137,9 +133,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 21ddab3917..8cb3aa18eb 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -65,11 +65,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -122,9 +118,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 2487b2f567..516866286d 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -70,11 +70,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -127,9 +123,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 2571215b38..4fc723064c 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -72,11 +72,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/early_setup_ss.h" #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -147,9 +143,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index e2f76cf608..e148d11a43 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -65,11 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/early_setup_ss.h" #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -144,9 +140,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index ed3df3f3c2..e5ac277fdd 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -71,11 +71,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/early_setup_ss.h" #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -197,9 +193,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 116ae0c6d3..86aff80fbd 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -65,11 +65,7 @@ static int spd_read_byte(u32 device, u32 address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> @@ -143,9 +139,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 1e439d45b4..6cc6b0e480 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -73,11 +73,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/early_setup_ss.h" #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -147,9 +143,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); |