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-rw-r--r--src/mainboard/google/storm/romstage.c2
-rw-r--r--src/soc/qualcomm/ipq806x/Makefile.inc1
-rw-r--r--src/soc/qualcomm/ipq806x/blobs_init.c78
-rw-r--r--src/soc/qualcomm/ipq806x/include/soc/soc_services.h26
-rw-r--r--src/soc/qualcomm/ipq806x/mbn_header.h37
5 files changed, 144 insertions, 0 deletions
diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c
index fb5b42e869..be8656b754 100644
--- a/src/mainboard/google/storm/romstage.c
+++ b/src/mainboard/google/storm/romstage.c
@@ -20,10 +20,12 @@
#include <cbmem.h>
#include <console/console.h>
#include <program_loading.h>
+#include <soc/soc_services.h>
void main(void)
{
console_init();
cbmem_initialize_empty();
+ initialize_dram();
run_ramstage();
}
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 0d5d59ca7f..7fb6290a42 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -33,6 +33,7 @@ verstage-y += timer.c
verstage-$(CONFIG_CONSOLE_SERIAL_IPQ806X) += uart.c
romstage-y += clock.c
+romstage-y += blobs_init.c
romstage-y += gpio.c
romstage-$(CONFIG_SPI_FLASH) += spi.c
romstage-y += timer.c
diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c
new file mode 100644
index 0000000000..96a14dc40b
--- /dev/null
+++ b/src/soc/qualcomm/ipq806x/blobs_init.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbfs.h>
+#include <string.h>
+#include <arch/cache.h>
+
+#include <soc/soc_services.h>
+
+#include <console/console.h>
+
+#include "mbn_header.h"
+
+static struct mbn_header *map_ipq_blob(const char *file_name)
+{
+ struct cbfs_file *blob_file;
+ struct mbn_header *blob_mbn;
+
+ blob_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, file_name);
+ if (!blob_file)
+ return NULL;
+
+ blob_mbn = (struct mbn_header *)((uintptr_t)blob_file +
+ ntohl(blob_file->offset));
+
+ /* some sanity checks on the headers */
+ if ((blob_mbn->mbn_version != 3) ||
+ (blob_mbn->mbn_total_size > ntohl(blob_file->len)))
+ return NULL;
+
+ return blob_mbn;
+}
+
+int initialize_dram(void)
+{
+ struct mbn_header *cdt_mbn;
+ struct mbn_header *ddr_mbn;
+ int (*ddr_init_function)(void *cdt_header);
+
+ cdt_mbn = map_ipq_blob("cdt.mbn");
+ ddr_mbn = map_ipq_blob("ddr.mbn");
+
+ if (!cdt_mbn || !ddr_mbn) {
+ printk(BIOS_ERR, "cdt.mbn: %p, ddr.mbn: %p\n",
+ cdt_mbn, ddr_mbn);
+ die("could not find DDR initialization blobs\n");
+ }
+
+ /* Actual area where DDR init is going to be running */
+ ddr_init_function = (int (*)(void *))ddr_mbn->mbn_destination;
+
+ /* Copy core into the appropriate memory location. */
+ memcpy(ddr_init_function, ddr_mbn + 1, ddr_mbn->mbn_total_size);
+ cache_sync_instructions();
+
+ if (ddr_init_function(cdt_mbn + 1) < 0) /* Skip mbn header. */
+ die("Fail to Initialize DDR\n");
+
+ printk(BIOS_INFO, "DDR initialized\n");
+
+ return 0;
+}
diff --git a/src/soc/qualcomm/ipq806x/include/soc/soc_services.h b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
new file mode 100644
index 0000000000..8a936fe7d9
--- /dev/null
+++ b/src/soc/qualcomm/ipq806x/include/soc/soc_services.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_QUALCOMM_IPQ806X_INCLUDE_SOC_SOC_SERVICES_H__
+#define __SOC_QUALCOMM_IPQ806X_INCLUDE_SOC_SOC_SERVICES_H__
+
+/* Returns zero on success, nonzero on failure. */
+int initialize_dram(void);
+
+#endif
diff --git a/src/soc/qualcomm/ipq806x/mbn_header.h b/src/soc/qualcomm/ipq806x/mbn_header.h
new file mode 100644
index 0000000000..6b27c71cf2
--- /dev/null
+++ b/src/soc/qualcomm/ipq806x/mbn_header.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_QUALCOMM_IPQ806X_MBN_HEADER_H__
+#define __SOC_QUALCOMM_IPQ806X_MBN_HEADER_H__
+
+#include <types.h>
+
+/* Qualcomm firmware blob header gleaned from util/ipqheader/ipqheader.py */
+
+struct mbn_header {
+ u32 mbn_type;
+ u32 mbn_version;
+ u32 mbn_source;
+ u32 mbn_destination;
+ u32 mbn_total_size;
+ u32 mbn_padding[5];
+};
+
+#endif
+