diff options
| -rw-r--r-- | Documentation/mainboard/index.md | 1 | ||||
| -rw-r--r-- | Documentation/mainboard/starlabs/starbook_adl.md | 86 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/Kconfig | 37 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/Kconfig.name | 3 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/dsdt.asl | 5 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/Makefile.inc | 9 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/board.fmd | 14 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/data.vbt | bin | 0 -> 8704 bytes | |||
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/devicetree.cb | 176 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/devtree.c | 56 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/gpio.c | 459 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/hda_verb.c | 74 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/romstage.c | 32 |
13 files changed, 947 insertions, 5 deletions
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 2e314e6b2d..134166f2e0 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -185,6 +185,7 @@ The boards in this section are not real mainboards, but emulators. - [StarLite Mk III](starlabs/lite_glk.md) - [StarLite Mk IV](starlabs/lite_glkr.md) - [StarBook Mk V](starlabs/starbook_tgl.md) +- [StarBook Mk VI](starlabs/starbook_adl.md) - [Flashing devices](starlabs/common/flashing.md) ## Supermicro diff --git a/Documentation/mainboard/starlabs/starbook_adl.md b/Documentation/mainboard/starlabs/starbook_adl.md new file mode 100644 index 0000000000..8e1a7c2309 --- /dev/null +++ b/Documentation/mainboard/starlabs/starbook_adl.md @@ -0,0 +1,86 @@ +# StarBook Mk V + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel i7-1260P (Alder Lake) + - Intel i3-1220P (Alder Lake) +- EC + - ITE IT5570E + - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel® Iris® Xe Graphics + - GOP driver is recommended, VBT is provided + - eDP 14-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 2 x DDR4 SODIMM +- Networking + - AX210 2230 WiFi / Bluetooth +- Sound + - Realtek ALC269-VB6 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD + - RTS5129 MicroSD card reader +- USB + - 1920x1080 CCD camera + - USB 3.1 Gen 2 (left) + - USB 3.1 Gen 2 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + - USB 2.0 Type-A (right) + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) +* Intel Management Engine firmware (me.bin) +* ITE Embedded Controller firmware (ec.bin) + +The files listed below are optional: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q256.V | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ + +Please see [here](../common/flashing.md) for instructions on how to flash with fwupd. diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index 0854c14bac..0d06c061b6 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -55,11 +55,29 @@ config BOARD_STARLABS_STARBOOK_TGL select SPI_FLASH_WINBOND select TPM_MEASURED_BOOT +config BOARD_STARLABS_STARBOOK_ADL + select BOARD_ROMSIZE_KB_32768 + select BOARD_STARLABS_STARBOOK_SERIES + select DRIVERS_INTEL_PMC + select EC_STARLABS_KBL_LEVELS + select EC_STARLABS_MAX_CHARGE + select EC_STARLABS_MIRROR_FLAG + select EC_STARLABS_NEED_ITE_BIN + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_ALDERLAKE + select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_ALDERLAKE_S3 + select SPI_FLASH_WINBOND + select TPM_MEASURED_BOOT + select PCIEXP_SUPPORT_RESIZABLE_BARS + if BOARD_STARLABS_STARBOOK_SERIES config CCD_PORT int default 6 if BOARD_STARLABS_LABTOP_CML + default 4 if BOARD_STARLABS_STARBOOK_ADL default 3 config CMOS_DEFAULT_FILE @@ -72,13 +90,13 @@ config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" config DIMM_SPD_SIZE - default 512 if BOARD_STARLABS_LABTOP_KBL + default 512 config DRIVER_TPM_SPI_CHIP default 2 config EC_GPE_SCI - default 0x6e if BOARD_STARLABS_STARBOOK_TGL + default 0x6e if BOARD_STARLABS_STARBOOK_TGL || BOARD_STARLABS_STARBOOK_ADL default 0x50 config EC_STARLABS_ADD_ITE_BIN @@ -93,6 +111,7 @@ config EC_VARIANT_DIR default "kbl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_KBL default "cml" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_CML default "tgl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_STARBOOK_TGL + default "adl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_STARBOOK_ADL config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" @@ -109,14 +128,16 @@ config MAINBOARD_FAMILY default "L3" if BOARD_STARLABS_LABTOP_KBL default "L4" if BOARD_STARLABS_LABTOP_CML default "B5" if BOARD_STARLABS_STARBOOK_TGL + default "B6-I" if BOARD_STARLABS_STARBOOK_ADL config MAINBOARD_PART_NUMBER default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL + default "StarBook Mk VI" if BOARD_STARLABS_STARBOOK_ADL config MAINBOARD_SMBIOS_PRODUCT_NAME - default "StarBook" if BOARD_STARLABS_STARBOOK_TGL + default "StarBook" if BOARD_STARLABS_STARBOOK_TGL || BOARD_STARLABS_STARBOOK_ADL default "LabTop" config ME_BIN_PATH @@ -127,15 +148,23 @@ config EDK2_BOOTSPLASH_FILE string default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" +config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS + default 32 + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n if BOARD_STARLABS_STARBOOK_ADL + config UART_FOR_CONSOLE + default 0 if BOARD_STARLABS_STARBOOK_ADL default 2 config USE_PM_ACPI_TIMER - default n if BOARD_STARLABS_STARBOOK_TGL + default n if BOARD_STARLABS_STARBOOK_TGL || BOARD_STARLABS_STARBOOK_ADL config VARIANT_DIR default "kbl" if BOARD_STARLABS_LABTOP_KBL default "cml" if BOARD_STARLABS_LABTOP_CML default "tgl" if BOARD_STARLABS_STARBOOK_TGL + default "adl" if BOARD_STARLABS_STARBOOK_ADL endif diff --git a/src/mainboard/starlabs/starbook/Kconfig.name b/src/mainboard/starlabs/starbook/Kconfig.name index 3db0d38554..50afad9c25 100644 --- a/src/mainboard/starlabs/starbook/Kconfig.name +++ b/src/mainboard/starlabs/starbook/Kconfig.name @@ -8,3 +8,6 @@ config BOARD_STARLABS_LABTOP_CML config BOARD_STARLABS_STARBOOK_TGL bool "Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)" + +config BOARD_STARLABS_STARBOOK_ADL + bool "Star Labs StarBook Mk VI (i3-1220P and i7-1260P)" diff --git a/src/mainboard/starlabs/starbook/dsdt.asl b/src/mainboard/starlabs/starbook/dsdt.asl index bee42358db..06889490ab 100644 --- a/src/mainboard/starlabs/starbook/dsdt.asl +++ b/src/mainboard/starlabs/starbook/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 + 0x20220930 ) { #include <acpi/dsdt_top.asl> @@ -30,6 +30,9 @@ DefinitionBlock( #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> +#elif CONFIG(SOC_INTEL_ALDERLAKE) + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> #endif /* PS/2 Keyboard */ diff --git a/src/mainboard/starlabs/starbook/variants/adl/Makefile.inc b/src/mainboard/starlabs/starbook/variants/adl/Makefile.inc new file mode 100644 index 0000000000..2a505c35c7 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/starlabs/starbook/variants/adl/board.fmd b/src/mainboard/starlabs/starbook/variants/adl/board.fmd new file mode 100644 index 0000000000..1d218f71e8 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl/board.fmd @@ -0,0 +1,14 @@ +FLASH 0x2000000 { + SI_ALL 0x1000000 { + SI_DESC 0x1000 + SI_ME + } + SI_BIOS 0x1000000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/starbook/variants/adl/data.vbt b/src/mainboard/starlabs/starbook/variants/adl/data.vbt Binary files differnew file mode 100644 index 0000000000..2c7db18510 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl/data.vbt diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb new file mode 100644 index 0000000000..fba073d049 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -0,0 +1,176 @@ +chip soc/intel/alderlake + # Graphics + # TODO: + # register "panel_cfg" = "{ + # .up_delay_ms = 200, // T3 + # .backlight_on_delay_ms = 0, // T7 + # .backlight_off_delay_ms = 50, // T9 + # .down_delay_ms = 0, // T10 + # .cycle_delay_ms = 500, // T12 + # .backlight_pwm_hz = 200, // PWM + # }" + + # FSP Memory + register "enable_c6dram" = "1" + register "sagv" = "SaGv_Enabled" + + # FSP Silicon + register "eist_enable" = "1" + + # Serial I/O + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + }" + + # Power + register "pch_slp_s3_min_assertion_width" = "2" # 50ms + register "pch_slp_s4_min_assertion_width" = "3" # 1s + register "pch_slp_sus_min_assertion_width" = "3" # 500ms + register "pch_slp_a_min_assertion_width" = "3" # 2s + + # PM Util + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_E" + + # Device Tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device ref igpu on + register "ddi_portA_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + end + device ref gna on end + device ref crashlog off end + device ref xhci on + # Motherboard USB Type C + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC3)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + + # Motherboard USB 3.0 + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + + # Daughterboard USB 3.0 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Internal Webcam + register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)" + + # Fingerprint Reader + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" + + # Daughterboard SD Card + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" + + # Internal Bluetooth + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" + end + device ref i2c0 on + chip drivers/i2c/hid + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E12_IRQ)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref shared_sram on end + device ref heci1 on end + device ref sata on + register "sata_salp_support" = "1" + register "sata_ports_enable[1]" = "1" + register "sata_ports_dev_slp[1]" = "1" + end + device ref pcie_rp5 on # WiFi + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypePciExpressGen3X1" + "SlotLengthShort" + "M.2/M 2230" + "SlotDataBusWidth1X" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "2" + device generic 0 on end + end + end + device ref pcie_rp9 on # SSD x4 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "srcclk_pin" = "1" + device generic 0 on end + end + end + device ref uart0 on end + device ref pch_espi on + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x00000381" + register "gen3_dec" = "0x00000511" + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.00 on end # IO Interface + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 on # PS/2 Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + end + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + device ref p2sb on end + device ref hda on + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + end +end diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c new file mode 100644 index 0000000000..d15b9a78aa --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <cpu/intel/turbo.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <option.h> +#include <types.h> +#include <variants.h> + +void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + + struct soc_power_limits_config *soc_conf_10core = + &cfg->power_limits_config[ADL_P_282_482_28W_CORE]; + + struct soc_power_limits_config *soc_conf_12core = + &cfg->power_limits_config[ADL_P_682_28W_CORE]; + + struct device *nic_dev = pcidev_on_root(0x1c, 4); + + /* Update PL1 & PL2 based on CMOS settings */ + switch (get_power_profile(PP_POWER_SAVER)) { + case PP_POWER_SAVER: + disable_turbo(); + soc_conf_10core->tdp_pl1_override = 15; + soc_conf_12core->tdp_pl1_override = 15; + soc_conf_10core->tdp_pl2_override = 15; + soc_conf_12core->tdp_pl2_override = 15; + // TODO:common_config->pch_thermal_trip = 20; + break; + case PP_BALANCED: + soc_conf_10core->tdp_pl1_override = 15; + soc_conf_12core->tdp_pl1_override = 15; + soc_conf_10core->tdp_pl2_override = 25; + soc_conf_12core->tdp_pl2_override = 25; + // TODO:common_config->pch_thermal_trip = 15; + break; + case PP_PERFORMANCE: + soc_conf_10core->tdp_pl1_override = 28; + soc_conf_12core->tdp_pl1_override = 28; + soc_conf_10core->tdp_pl2_override = 40; + soc_conf_12core->tdp_pl2_override = 40; + // TODO:common_config->pch_thermal_trip = 10; + break; + } + + /* Enable/Disable Wireless based on CMOS settings */ + if (get_uint_option("wireless", 1) == 0) + nic_dev->enabled = 0; + + /* Enable/Disable Webcam based on CMOS settings */ + if (get_uint_option("webcam", 1) == 0) + cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0; +} diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c new file mode 100644 index 0000000000..011316429a --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c @@ -0,0 +1,459 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variants.h> + +/* Early pad configuration in bootblock */ +const struct pad_config early_gpio_table[] = { + /* H10: UART0 RXD Debug Connector */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11: UART0 TXD Debug Connector */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + /* GPD0: Battery Low */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: Charger Connected */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN Wake */ + PAD_NC(GPD2, NONE), + /* GPD3: Power Button */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + /* GPD4: Sleep S3 */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: Sleep S4 */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: Sleep A */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: Power Adapter Disable */ + PAD_CFG_GPO(GPD7, 0, PWROK), + /* GPD8: Suspend Clock */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: Wireless LAN Sleep */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: Sleep S5 */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LAN PHY Enable */ + PAD_NC(GPD11, NONE), + + /* A0: ESPI IO 0 */ + /* A1: ESPI IO 1 */ + /* A2: ESPI IO 2 */ + /* A3: ESPI IO 3 */ + /* A4: ESPI CS 0 */ + /* A5: Not Connected */ + PAD_NC(GPP_A5, NONE), + /* A6: Not Connected */ + PAD_NC(GPP_A6, NONE), + /* A7: Embedded Controller SCI */ + PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, PLTRST, LEVEL), + /* A8: Not Connected */ + PAD_NC(GPP_A8, NONE), + /* A9: ESPI Clock */ + /* A10: ESPI Reset */ + /* A11: Not Connected */ + PAD_NC(GPP_A11, NONE), + /* A12: PCH M.2 SSD PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13: BlueTooth RF Kill */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14: Test Point 45 */ + PAD_NC(GPP_A14, NONE), + /* A15: Test Point 52 */ + PAD_NC(GPP_A15, NONE), + /* A16: USB OverCurrent 3 */ + PAD_NC(GPP_A16, NONE), + /* A17: Not Connected */ + PAD_NC(GPP_A17, NONE), + /* A18: DDI B DP HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19: TCP0 HPD */ + PAD_NC(GPP_A19, NONE), + /* A20: Test Point 44 */ + PAD_NC(GPP_A20, NONE), + /* A21: Fingerprint Reader Interrupt */ + PAD_NC(GPP_A21, NONE), + /* A22: Fingerprint Reader Reset */ + PAD_NC(GPP_A22, NONE), + /* A23: Not Connected */ + PAD_NC(GPP_A23, NONE), + + + /* B0: Core Vendor ID 0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1: Core Vendor ID 1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2: BC PROCHOT */ + PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* B3: Not Connected */ + PAD_NC(GPP_B3, NONE), + /* B4: Not Connected */ + PAD_NC(GPP_B4, NONE), + /* B5: I2C 2 SDA Touch Panel SDA */ + PAD_NC(GPP_B5, NONE), + /* B6: I2C 2 SCL Touch Panel Clock */ + PAD_NC(GPP_B6, NONE), + /* B7: I2C 3 SDA Test Point 15 */ + PAD_NC(GPP_B7, NONE), + /* B8: I2C 3 SCL Test Point 16 */ + PAD_NC(GPP_B8, NONE), + /* B9: Not Connected */ + PAD_NC(GPP_B9, NONE), + /* B10: Not Connected */ + PAD_NC(GPP_B10, NONE), + /* B11: I2C PMC PD Interrupt Test Point 28 */ + PAD_NC(GPP_B11, NONE), + /* B12: PM SLP S0 */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13: PLT RST */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14: Top Swap Override Weak Internal PD 20K + High: Enabled + Low: Disabled */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), + /* B15: Not Connected */ + PAD_NC(GPP_B15, NONE), + /* B16: Not Connected */ + PAD_NC(GPP_B16, NONE), + /* B17: Not Connected */ + PAD_NC(GPP_B17, NONE), + /* B18: Reboot Support Weak Internal PD 20K + High: Disabled + Low: Enabled */ + PAD_NC(GPP_B18, NONE), + /* B19: Not Connected */ + PAD_NC(GPP_B19, NONE), + /* B20: Not Connected */ + PAD_NC(GPP_B20, NONE), + /* B21: Not Connected */ + PAD_NC(GPP_B21, NONE), + /* B22: Not Connected */ + PAD_NC(GPP_B22, NONE), + /* B23: Not used MiPi Camera */ + PAD_NC(GPP_B23, NONE), + /* B24: Not Connected */ + PAD_NC(GPP_B24, NONE), + /* B25: Not Connected */ + PAD_NC(GPP_B25, NONE), + + /* C0: SMB Clock */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1: SMB Data */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2: TLS Confidentiality Weak Internal PD 20K + Low: Disabled + High: Enabled */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* C3: SML 0 Clock */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4: SML 0 Data */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5: Boot Strap Weak Internal PD 20K + Low: ESPI + High: Disabled */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + /* C6: SML 1 Clock */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* C7: SML 1 Data */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + /* C8: Not Connected */ + PAD_NC(GPP_C8, NONE), + /* C9: Not Connected */ + PAD_NC(GPP_C9, NONE), + /* C10: Not Connected */ + PAD_NC(GPP_C10, NONE), + /* C11: Not Connected */ + PAD_NC(GPP_C11, NONE), + /* C12: Not Connected */ + PAD_NC(GPP_C12, NONE), + /* C13: Not Connected */ + PAD_NC(GPP_C13, NONE), + /* C14: Not Connected */ + PAD_NC(GPP_C14, NONE), + /* C15: Not Connected */ + PAD_NC(GPP_C15, NONE), + /* C16: Not Connected */ + PAD_NC(GPP_C16, NONE), + /* C17: Not Connected */ + PAD_NC(GPP_C17, NONE), + /* C18: Not Connected */ + PAD_NC(GPP_C18, NONE), + /* C19: Not Connected */ + PAD_NC(GPP_C19, NONE), + /* C20: Not Connected */ + PAD_NC(GPP_C20, NONE), + /* C21: Not Connected */ + PAD_NC(GPP_C21, NONE), + /* C22: Not Connected */ + PAD_NC(GPP_C22, NONE), + /* C23: Not Connected */ + PAD_NC(GPP_C23, NONE), + + /* D0: Not used Audio ID 0 */ + PAD_NC(GPP_D0, NONE), + /* D1: Not used Audio ID 1 */ + PAD_NC(GPP_D1, NONE), + /* D2: Not used Audio ID 2 */ + PAD_NC(GPP_D2, NONE), + /* D3: Not Connected */ + PAD_NC(GPP_D3, NONE), + /* D4: Not Connected */ + PAD_NC(GPP_D4, NONE), + /* D5: Not Connected */ + PAD_NC(GPP_D5, NONE), + /* D6: Clock Request 1 PCH M.2 SSD */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7: Clock Request 2 Wireless LAN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8: Clock Request 3 LAN */ + PAD_NC(GPP_D8, NONE), + /* D9: GSPI 2 FPS */ + PAD_NC(GPP_D9, NONE), + /* D10: GSPI 2 Clock */ + PAD_NC(GPP_D10, NONE), + /* D11: GSPI 2 MISO FPS */ + PAD_NC(GPP_D11, NONE), + /* D12: GSPI 2 MOSI FPS */ + PAD_NC(GPP_D12, NONE), + /* D13: Wireless LAN Wake */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + /* D14: CPU M.2 SSD Power Enable */ + PAD_NC(GPP_D14, NONE), + /* D15: Not Connected */ + PAD_NC(GPP_D15, NONE), + /* D16: PCH M.2 SSD Power Enable */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* D17: Not used Fingerprint ID */ + PAD_NC(GPP_D17, NONE), + /* D18: Not Connected */ + PAD_NC(GPP_D18, NONE), + /* D19: Test Point 21 */ + PAD_NC(GPP_D19, NONE), + + /* E0: SATA x PCIe */ + PAD_NC(GPP_E0, NONE), + /* E1: Not used Accelerometer Interrupt */ + PAD_NC(GPP_E1, NONE), + /* E2: Not Connected */ + PAD_CFG_GPO(GPP_E2, 1, PLTRST), + /* E3: WiFi RF Kill */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4: Test Point 14 */ + PAD_NC(GPP_E4, NONE), + /* E5: Not Connected */ + PAD_NC(GPP_E5, NONE), + /* E6: JTAG ODT No internal PD + Low: Disabled + High: Enabled */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), + /* E7: Embedded Controller SMI */ + PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, DEEP, EDGE_SINGLE), + /* E8: DRAM Sleep */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + /* E9: USB OverCurrent 0 */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10: PWD Amplifier Input */ + PAD_CFG_GPO(GPP_E10, 0, PLTRST), + /* E11: TPM IRQ */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12: Touchpad Interrupt */ + PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST), + /* E13: Not connected */ + PAD_NC(GPP_E13, NONE), + /* E14: EDP HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15: Not Connected */ + PAD_NC(GPP_E15, NONE), + /* E16: Not Connected */ + PAD_NC(GPP_E16, NONE), + /* E17: Not Connected */ + PAD_CFG_GPO(GPP_E17, 1, PLTRST), + /* E18: Not Connected */ + PAD_NC(GPP_E18, NONE), + /* E19: Thunderbolt LSX RXD */ + PAD_NC(GPP_E19, NONE), + /* E20: Not Connected */ + PAD_NC(GPP_E20, NONE), + /* E21: Not Connected */ + PAD_NC(GPP_E21, NONE), + /* E22: Not Connected */ + PAD_NC(GPP_E22, NONE), + /* E23: Not Connected */ + PAD_NC(GPP_E23, NONE), + + /* F0: CNV BRI Data */ + PAD_NC(GPP_F0, NONE), + /* F1: CNV BRI Response */ + PAD_NC(GPP_F1, NONE), + /* F2: CNV RGI Data */ + PAD_NC(GPP_F2, NONE), + /* F3: CNV RGI Response */ + PAD_NC(GPP_F3, NONE), + /* F4: CNV RF Reset */ + PAD_NC(GPP_F4, NONE), + /* F5: Not used MODEM_CLKREQ */ + PAD_NC(GPP_F5, NONE), + /* F6: CNV PA Blanking */ + PAD_NC(GPP_F6, NONE), + /* F7: TBT LSX VCCIO Weak Internal PD 20K + Low: 1.8V + High: 3.3V */ + PAD_NC(GPP_F7, NONE), + /* F8: Not Connected */ + PAD_NC(GPP_F8, NONE), + /* F9: EC Sleep S0 */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* F10: Weak Internal PD 20K */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* F11: TPM ID */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), + /* F12: Not Connected */ + PAD_NC(GPP_F12, NONE), + /* F13: Not Connected */ + PAD_NC(GPP_F13, NONE), + /* F14: Not Connected */ + PAD_NC(GPP_F14, NONE), + /* F15: Not used Accelerometer Interrupt 2*/ + PAD_NC(GPP_F15, NONE), + /* F16: Not Connected */ + PAD_CFG_GPO(GPP_F16, 1, RSMRST), + /* F17: Not used Touch Panel Reset */ + PAD_NC(GPP_F17, NONE), + /* F18: Not used Touch Panel Interrupt */ + PAD_NC(GPP_F18, NONE), + /* F19: Not Connected */ + PAD_NC(GPP_F19, NONE), + /* F20: CPU M.2 SSD Reset */ + PAD_NC(GPP_F20, NONE), + /* F21: GPPC_F21 */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22: Not Connected */ + PAD_NC(GPP_F22, NONE), + /* F23: Not Connected */ + PAD_NC(GPP_F23, NONE), + + /* H0: PCH M.2 SSD Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* H2: Wireless LAN Reset */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* H3: Not Connected */ + PAD_NC(GPP_H3, NONE), + /* H4: I2C 0 SDA Touchpad */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: I2C 0 SDL Touchpad */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6: Not Connected */ + PAD_NC(GPP_H6, NONE), + /* H7: Not Connected */ + PAD_NC(GPP_H7, NONE), + /* H8: I2C 4 SDA GSensor */ + PAD_NC(GPP_H8, NONE), + /* H9: I2C 4 SDL GSensor */ + PAD_NC(GPP_H9, NONE), + /* H12: Not Connected */ + PAD_NC(GPP_H12, NONE), + /* H13: PCH M.2 SSD Device Sleep */ + PAD_CFG_GPO(GPP_H13, 0, PLTRST), + /* H14: Not Connected */ + PAD_NC(GPP_H14, NONE), + /* H15: DDPB Control Clock */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H16: Not Connected */ + PAD_NC(GPP_H16, NONE), + /* H17: DDPB Control Data */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18: CPI C10 Gate */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19: Clock Request 4 CPU M.2 SSD */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* H20: Not Connected */ + PAD_NC(GPP_H20, NONE), + /* H21: Not Connected */ + PAD_NC(GPP_H21, NONE), + /* H22: Not Connected */ + PAD_NC(GPP_H22, NONE), + /* H23: Not Connected */ + PAD_NC(GPP_H23, NONE), + + /* S0: Not Connected */ + PAD_NC(GPP_S0, NONE), + /* S1: Not Connected */ + PAD_NC(GPP_S1, NONE), + /* S2: DMIC Clock */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* S3: DMIC Data */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* S4: Not Connected */ + PAD_NC(GPP_S4, NONE), + /* S5: Not Connected */ + PAD_NC(GPP_S5, NONE), + /* S6: Not Connected */ + PAD_NC(GPP_S6, NONE), + /* S7: Not Connected */ + PAD_NC(GPP_S7, NONE), + + /* T0: Not Connected */ + PAD_NC(GPP_T0, NONE), + /* T1: Not Connected */ + PAD_NC(GPP_T1, NONE), + /* T2: Not Connected */ + PAD_NC(GPP_T2, NONE), + /* T3: Not Connected */ + PAD_NC(GPP_T3, NONE), + /* T4: Not Connected */ + PAD_NC(GPP_T4, NONE), + /* T5: Not Connected */ + PAD_NC(GPP_T5, NONE), + /* T6: Not Connected */ + PAD_NC(GPP_T6, NONE), + /* T7: Not Connected */ + PAD_NC(GPP_T7, NONE), + /* T8: Not Connected */ + PAD_NC(GPP_T8, NONE), + /* T9: Not Connected */ + PAD_NC(GPP_T9, NONE), + /* T10: Not Connected */ + PAD_NC(GPP_T10, NONE), + /* T11: Not Connected */ + PAD_NC(GPP_T11, NONE), + /* T12: Not Connected */ + PAD_NC(GPP_T12, NONE), + /* T13: Not Connected */ + PAD_NC(GPP_T13, NONE), + /* T14: Not Connected */ + PAD_NC(GPP_T14, NONE), + /* T15: Not Connected */ + PAD_NC(GPP_T15, NONE), + + /* R0: HDA BCLK */ + PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1), + /* R1: HDA SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* R2: HDA SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* R3: HDA SDI */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* R4: HDA Reset */ + PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), + /* R5: MiPi Cam Reset */ + PAD_NC(GPP_R5, NONE), + /* R6: Not Connected */ + PAD_NC(GPP_R6, NONE), + /* R7: Not Connected */ + PAD_NC(GPP_R7, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c new file mode 100644 index 0000000000..cc897ba2c0 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <stdint.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ + 0x1e507007, /* Subsystem ID */ + 36, /* Number of jacks (NID entries) */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID Verb-table */ + AZALIA_SUBVENDOR(0, 0x1e507007), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x17, 0x042B1010), + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + AZALIA_PIN_CFG(0, 0x19, 0x04AB1020), + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1d, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + AZALIA_PIN_CFG(0, 0x21, 0x042b1010), + + /* ALC269 Default 1 */ + 0x02050011, + 0x02041410, + 0x02050012, + 0x02042901, + + /* ALC269 Default 2 */ + 0x0205000d, + 0x02044440, + 0x02050007, + 0x02040040, + + /* ALC269 Default 3 */ + 0x02050002, + 0x0204aab8, + 0x02050008, + 0x02040300, + + /* ALC269 Default 4 */ + 0x02050017, + 0x020400af, + 0x02050005, + 0x020400c0, + + 0x80862815, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 9, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18561010), + AZALIA_PIN_CFG(2, 0x0a, 0x18561010), + AZALIA_PIN_CFG(2, 0x0b, 0x18561010), + AZALIA_PIN_CFG(2, 0x0c, 0x18561010), + AZALIA_PIN_CFG(2, 0x0d, 0x18561010), + AZALIA_PIN_CFG(2, 0x0e, 0x18561010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/starbook/variants/adl/romstage.c b/src/mainboard/starlabs/starbook/variants/adl/romstage.c new file mode 100644 index 0000000000..a3c49ead96 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl/romstage.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <types.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR4, + }; + + const bool half_populated = false; + + const struct mem_spd ddr4_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); + + const uint8_t vtd = get_uint_option("vtd", 1); + mupd->FspmConfig.VtdDisable = !vtd; +}; |