diff options
| -rw-r--r-- | src/soc/rockchip/rk3399/clock.c | 21 |
1 files changed, 6 insertions, 15 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 182e398e64..75af695b68 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -249,14 +249,8 @@ enum { CLK_I2C3_DIV_CON_SHIFT = 0, /* CRU_SOFTRST_CON4 */ - RESETN_DDR0_REQ_MASK = 1, - RESETN_DDR0_REQ_SHIFT = 8, - RESETN_DDRPHY0_REQ_MASK = 1, - RESETN_DDRPHY0_REQ_SHIFT = 9, - RESETN_DDR1_REQ_MASK = 1, - RESETN_DDR1_REQ_SHIFT = 12, - RESETN_DDRPHY1_REQ_MASK = 1, - RESETN_DDRPHY1_REQ_SHIFT = 13, +#define RESETN_DDR_REQ_SHIFT(ch) (8 + (ch) * 4) +#define RESETN_DDRPHY_REQ_SHIFT(ch) (9 + (ch) * 4) }; #define VCO_MAX_KHZ (3200 * (MHz / KHz)) @@ -650,14 +644,11 @@ void rkclk_configure_ddr(unsigned int hz) rkclk_set_dpllssc(&dpll_cfg); } -#define CRU_SFTRST_DDR_CTRL(ch, n) ((1 << 16 | (n)) << (8 + (ch) * 4)) -#define CRU_SFTRST_DDR_PHY(ch, n) ((1 << 16 | (n)) << (9 + (ch) * 4)) - -void rkclk_ddr_reset(u32 channel, u32 ctl, u32 phy) +void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy) { - write32(&cru_ptr->softrst_con[4], - CRU_SFTRST_DDR_CTRL(channel, ctl) | - CRU_SFTRST_DDR_PHY(channel, phy)); + write32(&cru_ptr->softrst_con[4], RK_CLRSETBITS( + 1 << RESETN_DDR_REQ_SHIFT(ch) | 1 << RESETN_DDRPHY_REQ_SHIFT(ch), + ctl << RESETN_DDR_REQ_SHIFT(ch) | phy << RESETN_DDRPHY_REQ_SHIFT(ch))); } #define SPI_CLK_REG_VALUE(bus, clk_div) \ |