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-rw-r--r--payloads/libpayload/drivers/timer/Kconfig5
-rw-r--r--src/soc/mediatek/common/include/soc/timer.h19
-rw-r--r--src/soc/mediatek/common/timer.c27
-rw-r--r--src/soc/mediatek/mt8173/timer.c2
4 files changed, 35 insertions, 18 deletions
diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig
index f1542cf9db..5a61dfab51 100644
--- a/payloads/libpayload/drivers/timer/Kconfig
+++ b/payloads/libpayload/drivers/timer/Kconfig
@@ -54,7 +54,7 @@ config TIMER_IMG_PISTACHIO
bool "Timer for IMG Pistachio"
config TIMER_MTK
- bool "Timer for MediaTek MT8173"
+ bool "Timer for MediaTek"
endchoice
@@ -77,7 +77,7 @@ config TIMER_GENERIC_REG
default 0x004A2000 if TIMER_IPQ40XX
default 0x0200A028 if TIMER_IPQ806X
default 0x101C0100 if TIMER_MCT
- default 0x10008048 if TIMER_MTK
+ default 0x10008068 if TIMER_MTK
default 0xff810028 if TIMER_RK3288
default 0xff850008 if TIMER_RK3399
default 0x60005010 if TIMER_TEGRA_1US
@@ -89,6 +89,7 @@ config TIMER_GENERIC_HIGH_REG
hex "Generic Timer High Register Address"
default 0x004A2004 if TIMER_IPQ40XX
default 0x101C0104 if TIMER_MCT
+ default 0x10008078 if TIMER_MTK
default 0xff81002C if TIMER_RK3288
default 0xff85000C if TIMER_RK3399
default 0x0
diff --git a/src/soc/mediatek/common/include/soc/timer.h b/src/soc/mediatek/common/include/soc/timer.h
index babcbba561..b58d4d3227 100644
--- a/src/soc/mediatek/common/include/soc/timer.h
+++ b/src/soc/mediatek/common/include/soc/timer.h
@@ -19,18 +19,21 @@
#include <soc/addressmap.h>
#include <types.h>
-#define GPT4_MHZ 13
+#define GPT_MHZ 13
struct mtk_gpt_regs {
- u32 reserved[16];
- u32 gpt4_con;
- u32 gpt4_clk;
- u32 gpt4_cnt;
+ u32 reserved1[24];
+ u32 gpt6_con;
+ u32 gpt6_clk;
+ u32 gpt6_cnt_l;
+ u32 reserved2[3];
+ u32 gpt6_cnt_h;
};
-check_member(mtk_gpt_regs, gpt4_con, 0x0040);
-check_member(mtk_gpt_regs, gpt4_clk, 0x0044);
-check_member(mtk_gpt_regs, gpt4_cnt, 0x0048);
+check_member(mtk_gpt_regs, gpt6_con, 0x0060);
+check_member(mtk_gpt_regs, gpt6_clk, 0x0064);
+check_member(mtk_gpt_regs, gpt6_cnt_l, 0x0068);
+check_member(mtk_gpt_regs, gpt6_cnt_h, 0x0078);
enum {
GPT_CON_EN = 0x01,
diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c
index 0762c2b4b4..c8af2be113 100644
--- a/src/soc/mediatek/common/timer.c
+++ b/src/soc/mediatek/common/timer.c
@@ -25,21 +25,34 @@ static struct mtk_gpt_regs *const mtk_gpt = (void *)GPT_BASE;
__weak void timer_prepare(void) { /* do nothing */ }
+static uint64_t timer_raw_value(void)
+{
+ /*
+ * According to "General-Purpose Timer (GPT).pdf", The read operation of
+ * gpt6_cnt_l will make gpt6_cnt_h fixed until the next read operation
+ * of gpt6_cnt_l. Therefore, we must read gpt6_cnt_l before gpt6_cnt_h.
+ */
+ uint32_t low = read32(&mtk_gpt->gpt6_cnt_l);
+ uint32_t high = read32(&mtk_gpt->gpt6_cnt_h);
+
+ return low | (uint64_t)high << 32;
+}
+
void timer_monotonic_get(struct mono_time *mt)
{
- mono_time_set_usecs(mt, read32(&mtk_gpt->gpt4_cnt) / GPT4_MHZ);
+ mono_time_set_usecs(mt, timer_raw_value() / GPT_MHZ);
}
void init_timer(void)
{
timer_prepare();
- /* Disable GPT4 and clear the counter */
- clrbits_le32(&mtk_gpt->gpt4_con, GPT_CON_EN);
- setbits_le32(&mtk_gpt->gpt4_con, GPT_CON_CLR);
+ /* Disable timer and clear the counter */
+ clrbits_le32(&mtk_gpt->gpt6_con, GPT_CON_EN);
+ setbits_le32(&mtk_gpt->gpt6_con, GPT_CON_CLR);
/* Set clock source to system clock and set clock divider to 1 */
- write32(&mtk_gpt->gpt4_clk, GPT_SYS_CLK | GPT_CLK_DIV1);
- /* Set operation mode to FREERUN mode and enable GTP4 */
- write32(&mtk_gpt->gpt4_con, GPT_CON_EN | GPT_MODE_FREERUN);
+ write32(&mtk_gpt->gpt6_clk, GPT_SYS_CLK | GPT_CLK_DIV1);
+ /* Set operation mode to FREERUN mode and enable timer */
+ write32(&mtk_gpt->gpt6_con, GPT_CON_EN | GPT_MODE_FREERUN);
}
diff --git a/src/soc/mediatek/mt8173/timer.c b/src/soc/mediatek/mt8173/timer.c
index 2c9995ac05..eb2a1424b2 100644
--- a/src/soc/mediatek/mt8173/timer.c
+++ b/src/soc/mediatek/mt8173/timer.c
@@ -31,5 +31,5 @@ void timer_prepare(void)
*/
write32(&mt8173_mcucfg->xgpt_idx, 0);
/* Set clock mode to 13Mhz and enable XGPT */
- write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT4_MHZ) << 8)));
+ write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT_MHZ) << 8)));
}