diff options
| -rw-r--r-- | src/mainboard/google/brya/acpi/power.asl | 18 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/variant.c | 6 |
2 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl index c69f21ab88..e441530165 100644 --- a/src/mainboard/google/brya/acpi/power.asl +++ b/src/mainboard/google/brya/acpi/power.asl @@ -170,25 +170,25 @@ Method (PGOF, 0, Serialized) /* All rails are about to go down */ \_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG) - /* Ramp down NV33 and let rail discharge to <10% */ - \_SB.PCI0.CTXS (GPIO_NV33_PWR_EN) - GPPL (GPIO_NV33_PG, 0, 20) - Sleep (15) + /* Ramp down FBVDD (active-low) and let rail discharge to <10% */ + \_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN) + GPPL (GPIO_FBVDD_PG, 0, 20) + Sleep (150) /* Ramp down PEXVDD and let rail discharge to <10% */ \_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN) GPPL (GPIO_PEXVDD_PG, 0, 20) - Sleep (2) + Sleep (10) /* Ramp down NVVDD and let rail discharge to <10% */ \_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN) GPPL (GPIO_NVVDD_PG, 0, 20) Sleep (2) - /* Ramp down FBVDD (active-low) and let rail discharge to <10% */ - \_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN) - GPPL (GPIO_FBVDD_PG, 0, 20) - Sleep (150) + /* Ramp down NV33 and let rail discharge to <10% */ + \_SB.PCI0.CTXS (GPIO_NV33_PWR_EN) + GPPL (GPIO_NV33_PG, 0, 20) + Sleep (4) /* Ramp down 1.8V */ \_SB.PCI0.CTXS (GPIO_1V8_PWR_EN) diff --git a/src/mainboard/google/brya/variants/agah/variant.c b/src/mainboard/google/brya/variants/agah/variant.c index cc9389284c..73fe75bc20 100644 --- a/src/mainboard/google/brya/variants/agah/variant.c +++ b/src/mainboard/google/brya/variants/agah/variant.c @@ -56,10 +56,10 @@ static const struct power_rail_sequence gpu_on_seq[] = { /* In GCOFF entry order (i.e., power-off order) */ static const struct power_rail_sequence gpu_off_seq[] = { - { "NV3_3", NV33_PWR_EN, false, NV33_PG, 15,}, - { "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, 2,}, - { "NVVDD+MSVDD", NVVDD_PWR_EN, false, NVVDD_PG, 2,}, { "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 150,}, + { "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, 10,}, + { "NVVDD+MSVDD", NVVDD_PWR_EN, false, NVVDD_PG, 2,}, + { "NV3_3", NV33_PWR_EN, false, NV33_PG, 4,}, { "GPU 1.8V", GPU_1V8_PWR_EN, false, GPU_1V8_PG, 0,}, }; |