diff options
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 611a61035d..bdcd357173 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -17,6 +17,11 @@ #include <soc/soc_chip.h> #include <string.h> +/* THC assignment definition */ +#define THC_NONE 0 +#define THC_0 1 +#define THC_1 2 + /* * Chip config parameter PcieRpL1Substates uses (UPD value + 1) * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. @@ -221,6 +226,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->VmdEnable = 0; + /* THC */ + dev = pcidev_path_on_root(PCH_DEVFN_THC0); + if (!dev) + params->ThcPort0Assignment = 0; + else + params->ThcPort0Assignment = dev->enabled ? THC_0 : THC_NONE; + + dev = pcidev_path_on_root(PCH_DEVFN_THC1); + if (!dev) + params->ThcPort1Assignment = 0; + else + params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; |