diff options
| -rw-r--r-- | src/soc/intel/denverton_ns/chip.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/fiamux.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/fiamux.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/romstage.c | 16 |
4 files changed, 14 insertions, 27 deletions
diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 9547bec275..a43504cb29 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 - 2017 Intel Corp. + * Copyright (C) 2017 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,8 +32,6 @@ #include <soc/ramstage.h> #include <soc/fiamux.h> #include <spi-generic.h> -#include <hsio.h> -#include <harcuvar_boardid.h> static void pci_domain_set_resources(device_t dev) { @@ -74,7 +73,6 @@ static void soc_silicon_init_params(FSPS_UPD *silupd) { size_t num; uint16_t supported_hsio_lanes; - uint8_t boardid = board_id(); BL_HSIO_INFORMATION *hsio_config; BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data(); @@ -82,16 +80,7 @@ static void soc_silicon_init_params(FSPS_UPD *silupd) supported_hsio_lanes = (uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed; - switch (boardid) { - case BoardIdHarcuvar: - num = ARRAY_SIZE(harcuvar_hsio_config); - hsio_config = (BL_HSIO_INFORMATION *)harcuvar_hsio_config; - break; - default: - num = 0; - hsio_config = NULL; - break; - } + num = mainboard_get_hsio_config(&hsio_config); if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config)) die("HSIO Configuration is invalid, please correct it!"); diff --git a/src/soc/intel/denverton_ns/fiamux.c b/src/soc/intel/denverton_ns/fiamux.c index 282ba030e8..36b8223d04 100644 --- a/src/soc/intel/denverton_ns/fiamux.c +++ b/src/soc/intel/denverton_ns/fiamux.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 - 2017 Intel Corporation + * Copyright (C) 2017 Online SAS * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -138,3 +139,9 @@ BL_FIA_MUX_CONFIG_HOB *get_fiamux_hob_data(void) return fiamux_hob_data; } + +__attribute__((weak)) size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) +{ + *p_hsio_config = NULL; + return 0; +} diff --git a/src/soc/intel/denverton_ns/include/soc/fiamux.h b/src/soc/intel/denverton_ns/include/soc/fiamux.h index e8aaf65f11..3fd9321e07 100644 --- a/src/soc/intel/denverton_ns/include/soc/fiamux.h +++ b/src/soc/intel/denverton_ns/include/soc/fiamux.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,4 +25,6 @@ int get_fiamux_hsio_info(uint16_t num_of_lanes, size_t num_of_entry, BL_FIA_MUX_CONFIG_HOB *get_fiamux_hob_data(void); void print_fiamux_config_hob(BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data); +size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config); + #endif // _MAINBOARD_HARCUVAR_FIAMUX_H diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 512d8ccb3c..e0286f3f01 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 - 2017 Intel Corp. + * Copyright (C) 2017 Online SAS. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,8 +17,6 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <harcuvar_boardid.h> -#include <hsio.h> #include <reset.h> #include <soc/fiamux.h> #include <soc/iomap.h> @@ -237,7 +236,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) FSPM_UPD *mupd = container_of(m_cfg, FSPM_UPD, FspmConfig); size_t num; uint16_t supported_hsio_lanes; - uint8_t boardid = board_id(); BL_HSIO_INFORMATION *hsio_config; /* Set the parameters for MemoryInit */ @@ -250,17 +248,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) /* Assume the validating silicon has max lanes. */ supported_hsio_lanes = BL_ME_FIA_MUX_LANE_NUM_MAX; - switch (boardid) { - case BoardIdHarcuvar: - num = ARRAY_SIZE(harcuvar_hsio_config); - hsio_config = - (BL_HSIO_INFORMATION *)harcuvar_hsio_config; - break; - default: - num = 0; - hsio_config = NULL; - break; - } + num = mainboard_get_hsio_config(&hsio_config); if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config)) |