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-rw-r--r--src/arch/x86/cpu.c2
-rw-r--r--src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl6
-rw-r--r--src/northbridge/amd/agesa/family15tn/northbridge.c2
-rw-r--r--src/northbridge/amd/agesa/family16kb/northbridge.c2
-rw-r--r--src/northbridge/amd/pi/00630F01/northbridge.c2
-rw-r--r--src/northbridge/amd/pi/00660F01/northbridge.c2
-rw-r--r--src/northbridge/amd/pi/00730F01/northbridge.c2
-rw-r--r--src/soc/intel/baytrail/include/soc/gpio.h14
-rw-r--r--src/soc/intel/broadwell/smi.c2
-rw-r--r--src/southbridge/intel/i82801dx/smi.c2
-rw-r--r--src/southbridge/intel/i82801ix/smi.c2
-rw-r--r--src/southbridge/intel/i82870/82870.h2
-rw-r--r--src/southbridge/intel/i82870/ioapic.c4
-rw-r--r--src/southbridge/intel/lynxpoint/smi.c2
14 files changed, 23 insertions, 23 deletions
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 4c1bce05d6..8f8fdc1fd0 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -211,7 +211,7 @@ static void set_cpu_ops(struct device *cpu)
cpu->ops = driver ? driver->ops : NULL;
}
-/* Keep track of default apic ids for SMM. */
+/* Keep track of default APIC ids for SMM. */
static int cpus_default_apic_id[CONFIG_MAX_CPUS];
/*
diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
index 353080194f..e46611d219 100644
--- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
+++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
@@ -22,13 +22,13 @@ Scope(\_SB) {
/* Methods called by run-time generated SSDT Processor objects */
Method(CPMA, 1, NotSerialized) {
- // _MAT method - create an madt apic buffer
+ // _MAT method - create an madt APIC buffer
// Arg0 = Processor ID = Local APIC ID
// Local0 = CPON flag for this cpu
Store(DerefOf(Index(CPON, Arg0)), Local0)
- // Local1 = Buffer (in madt apic form) to return
+ // Local1 = Buffer (in madt APIC form) to return
Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
- // Update the processor id, lapic id, and enable/disable status
+ // Update the processor id, Local APIC id, and enable/disable status
Store(Arg0, Index(Local1, 2))
Store(Arg0, Index(Local1, 3))
Store(Local0, Index(Local1, 4))
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 3519ab0e5b..642fc150e1 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -859,7 +859,7 @@ static void cpu_bus_scan(struct device *dev)
* in LocalApicInitializationAtEarly() function.
* And reference GetLocalApicIdForCore()
*
- * Apply apic enumeration rules
+ * Apply APIC enumeration rules
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
* put the local-APICs at m..z
*
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 96d71cdc18..fcd7ec1fe6 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -886,7 +886,7 @@ static void cpu_bus_scan(struct device *dev)
* in LocalApicInitializationAtEarly() function.
* And reference GetLocalApicIdForCore()
*
- * Apply apic enumeration rules
+ * Apply APIC enumeration rules
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
* put the local-APICs at m..z
*
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index 2df105a4fb..28502b0017 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -864,7 +864,7 @@ static void cpu_bus_scan(struct device *dev)
* in LocalApicInitializationAtEarly() function.
* And reference GetLocalApicIdForCore()
*
- * Apply apic enumeration rules
+ * Apply APIC enumeration rules
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
* put the local-APICs at m..z
*
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 855936af79..0a1b0ba1a4 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -871,7 +871,7 @@ static void cpu_bus_scan(struct device *dev)
* in LocalApicInitializationAtEarly() function.
* And reference GetLocalApicIdForCore()
*
- * Apply apic enumeration rules
+ * Apply APIC enumeration rules
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
* put the local-APICs at m..z
*
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 8f23e682e1..05c5142a70 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -1130,7 +1130,7 @@ static void cpu_bus_scan(struct device *dev)
* in LocalApicInitializationAtEarly() function.
* And reference GetLocalApicIdForCore()
*
- * Apply apic enumeration rules
+ * Apply APIC enumeration rules
* For systems with >= 16 APICs, put the IO-APICs at 0..n and
* put the local-APICs at m..z
*
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h
index d6be80fde2..3c1e7f37dd 100644
--- a/src/soc/intel/baytrail/include/soc/gpio.h
+++ b/src/soc/intel/baytrail/include/soc/gpio.h
@@ -196,49 +196,49 @@
.io_sel = GPIO_DIR_INPUT, \
.is_gpio = 1 }
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
#define GPIO_DIRQ \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
| PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
#define GPIO_DIRQ_LEVELHIGH_NO_PULL \
{ .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
| PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
#define GPIO_DIRQ_LEVELLOW_PU_20K \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
| PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
#define GPIO_DIRQ_EDGELOW_PU_20K \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
| PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
#define GPIO_DIRQ_EDGEHIGH_PD_20K \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \
| PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
#define GPIO_DIRQ_EDGELOW_PD_20K \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \
| PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
#define GPIO_DIRQ_EDGEBOTH_PU_20K \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
| PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \
diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c
index b26700e267..b1be1faa69 100644
--- a/src/soc/intel/broadwell/smi.c
+++ b/src/soc/intel/broadwell/smi.c
@@ -71,7 +71,7 @@ static void __unused southbridge_trigger_smi(void)
* - Writes to io 0xb2 (APMC)
* - Writes to the Local Apic ICR with Delivery mode SMI.
*
- * Using the local apic is a bit more tricky. According to
+ * Using the local APIC is a bit more tricky. According to
* AMD Family 11 Processor BKDG no destination shorthand must be
* used.
* The whole SMM initialization is quite a bit hardware specific, so
diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c
index 0de98aca9a..26dfc60e5b 100644
--- a/src/southbridge/intel/i82801dx/smi.c
+++ b/src/southbridge/intel/i82801dx/smi.c
@@ -305,7 +305,7 @@ static void aseg_smm_relocate(void)
* - Writes to io 0xb2 (APMC)
* - Writes to the Local Apic ICR with Delivery mode SMI.
*
- * Using the local apic is a bit more tricky. According to
+ * Using the local APIC is a bit more tricky. According to
* AMD Family 11 Processor BKDG no destination shorthand must be
* used.
* The whole SMM initialization is quite a bit hardware specific, so
diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c
index 25d3515134..6e7463fcd3 100644
--- a/src/southbridge/intel/i82801ix/smi.c
+++ b/src/southbridge/intel/i82801ix/smi.c
@@ -111,7 +111,7 @@ static void aseg_smm_relocate(void)
* - Writes to io 0xb2 (APMC)
* - Writes to the Local Apic ICR with Delivery mode SMI.
*
- * Using the local apic is a bit more tricky. According to
+ * Using the local APIC is a bit more tricky. According to
* AMD Family 11 Processor BKDG no destination shorthand must be
* used.
* The whole SMM initialization is quite a bit hardware specific, so
diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h
index 1fe40b6e6f..ce76db0682 100644
--- a/src/southbridge/intel/i82870/82870.h
+++ b/src/southbridge/intel/i82870/82870.h
@@ -11,7 +11,7 @@
* GNU General Public License for more details.
*/
-/* for io apic 1461 */
+/* for io APIC 1461 */
#define MBAR 0x10
#define ABAR 0x40
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index 4fbf329342..1f4aa501a8 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -43,8 +43,8 @@ static void p64h2_ioapic_init(struct device *dev)
uint32_t memoryBase;
int apic_index, apic_id;
- volatile uint32_t *pIndexRegister; /* io apic io memory space command address */
- volatile uint32_t *pWindowRegister; /* io apic io memory space data address */
+ volatile uint32_t *pIndexRegister; /* io APIC io memory space command address */
+ volatile uint32_t *pWindowRegister; /* io APIC io memory space data address */
apic_index = num_p64h2_ioapics;
num_p64h2_ioapics++;
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index ed3c6cce7b..6aef493ee1 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -76,7 +76,7 @@ static void __unused southbridge_trigger_smi(void)
* - Writes to io 0xb2 (APMC)
* - Writes to the Local Apic ICR with Delivery mode SMI.
*
- * Using the local apic is a bit more tricky. According to
+ * Using the local APIC is a bit more tricky. According to
* AMD Family 11 Processor BKDG no destination shorthand must be
* used.
* The whole SMM initialization is quite a bit hardware specific, so
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 19:02:19 +0000