3 files changed, 44 insertions, 0 deletions

diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 4f3a202914..81b2c24569 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -6,6 +6,7 @@ subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
+subdirs-y += ../../../cpu/intel/turbo
 
 ramstage-y += memmap.c
 romstage-y += memmap.c
diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/baytrail/msr.h
index 5094f965c7..462f24990c 100644
--- a/src/soc/intel/baytrail/baytrail/msr.h
+++ b/src/soc/intel/baytrail/baytrail/msr.h
@@ -23,9 +23,17 @@
 #define MSR_IA32_PLATFORM_ID		0x17
 #define MSR_BSEL_CR_OVERCLOCK_CONTROL	0xcd
 #define MSR_PLATFORM_INFO		0xce
+#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_POWER_MISC			0x120
 #define MSR_IA32_PERF_CTL		0x199
 #define MSR_IA32_MISC_ENABLES		0x1a0
+#define MSR_POWER_CTL			0x1fc
+#define MSR_PKG_POWER_SKU_UNIT		0x606
+#define MSR_PKG_POWER_LIMIT		0x610
 #define MSR_IACORE_RATIOS		0x66a
 #define MSR_IACORE_VIDS			0x66b
+#define MSR_PKG_TURBO_CFG1		0x670
+#define MSR_CPU_TURBO_WKLD_CFG1		0x671
+#define MSR_CPU_TURBO_WKLD_CFG2		0x672
 
 #endif /* _BAYTRAIL_IOSF_H_ */
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index c55053103c..e3bdc422e0 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -21,13 +21,16 @@
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/turbo.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
+#include <reg_script.h>
 
+#include <baytrail/msr.h>
 #include <baytrail/pattrs.h>
 #include <baytrail/ramstage.h>
 #include <baytrail/smm.h>
@@ -48,6 +51,26 @@ static int adjust_apic_id(int index, int apic_id)
 	return 2 * index;
 }
 
+/* Package level MSRs */
+const struct reg_script package_msr_script[] = {
+	/* Set Package TDP to ~7W */
+	REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa),
+	REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702),
+	REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b),
+	REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0),
+	REG_SCRIPT_END
+};
+
+/* Core level MSRs */
+const struct reg_script core_msr_script[] = {
+	/* Dynamic L2 shrink enable and threshold */
+	REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008),
+	/* Disable C1E */
+	REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
+	REG_MSR_OR(MSR_POWER_MISC, 0x44),
+	REG_SCRIPT_END
+};
+
 void baytrail_init_cpus(device_t dev)
 {
 	struct bus *cpu_bus = dev->link_list;
@@ -66,6 +89,12 @@ void baytrail_init_cpus(device_t dev)
 	mp_params.num_records = ARRAY_SIZE(mp_steps);
 	mp_params.microcode_pointer = pattrs->microcode_patch;
 
+	/* Set package MSRs */
+	reg_script_run(package_msr_script);
+
+	/* Enable Turbo/Burst Mode */
+	enable_turbo();
+
 	if (mp_init(cpu_bus, &mp_params)) {
 		printk(BIOS_ERR, "MP initialization failure.\n");
 	}
@@ -74,6 +103,12 @@ void baytrail_init_cpus(device_t dev)
 static void baytrail_core_init(device_t cpu)
 {
 	printk(BIOS_DEBUG, "Init BayTrail core.\n");
+
+	/* Set core MSRs */
+	reg_script_run(core_msr_script);
+
+	/* Set this core to max frequency ratio */
+	set_max_freq();
 }
 
 static struct device_operations cpu_dev_ops = {