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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2021-04-30 17:15:28 +0530
committerFelix Held <felix-coreboot@felixheld.de>2021-05-05 22:40:44 +0000
commitcc3637f177c5f1264c43a9aee625bd505e07a92d (patch)
tree4bbb0ba36d1ddd06fee7fd5ec142b5ca6272ef9a /util/spd_tools
parentc616fd5b7ab7939f9a250eb41f27972fcaaa8f0f (diff)
soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 reg
Earlier we did not have definition for BIT27 for PAD_CFG0 register, we will use this BIT to enable "virtual wire messaging for native function" If this bit is enabled, whenever change is detected on the pad, virtual wire message is generated and sent to destination set by native function. This bit must be set while enabling CPU PCIe root port programming for ADL and thus defining a new macro to set native pad function along with NAF_VWE bit to make GPIO programming easier from coreboot. BUG=None BRANCH=None TEST=Code compilation works fine and if we use this macro to program GPIO, proper bit is getting set in PAD_CFG register Change-Id: I732e68b413eb01b8ae1a4927836762c8875b73d2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52782 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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