soc/intel/alderlake: Rework the GPIO PAD Pin numbers

This patch creates a `relative increment by 1` macro to let SoC
gpio pad configuration to be more flexible while adding support
for newer PCH SoC.

With this changes adding GPIO controller support for PCH-N would
become really simple without too much of code duplication.

For example: ADL-N has added `GPP_I` pins into community 1 hence,
the additional code for `PCH-N` whould appear incremetal to ADL-P.

> #define GPP_B			0x0
> #define GPP_T			INC(GPP_B)
> #define GPP_A			INC(GPP_T)
> #define GPP_R			INC(GPP_A)
> #define GPD			INC(GPP_R)
> #define GPP_S			INC(GPD)
> if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
> #define GPP_I			INC(GPP_S)
> #define GPP_H			INC(GPP_I)
> #else
> #define GPP_H			INC(GPP_S)
> #endif
> #define GPP_D			INC(GPP_H)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie3b2183381b877da0a6e5a27f5176f0e21e0c9fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

0 files changed, 0 insertions, 0 deletions