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author | Nico Huber <nico.h@gmx.de> | 2019-10-08 19:41:40 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2019-10-29 10:46:41 +0000 |
commit | 21961fc0923faee368a7244ef956669505a40b43 (patch) | |
tree | 47194bb2dda4846e09470e9aa08ccdb4744a2b45 /util/romcc/romcc.c | |
parent | 7f57dd4b654f001cfcdd34b6faa05a2d5b89576c (diff) |
3rdparty/libgfxinit: Update submodule pointer
This includes a huge set of refactorings to support Core Display Clock
(CDClk) frequency switching based on the current mode requirements.
The CDClk is configurable since Haswell and runtime switching is suppor-
ted since Broadwell. Always using the lowest possible frequency setting
should allow some power-savings. While, on the upper end, we can support
higher resolution panels now, without having to change the static confi-
guration.
There have also been some smaller changes and fixes, including:
o Parsing of eDP 1.4+ DPCD link rates, enables panels that don't
advertise a maximum link rate but only individual ones.
o DP support for Ibex Peak.
o Corrected limit for HDMI on G45 to 165MHz.
o Reworked GMBUS reset handling and timeouts, should help with
stalled GMBUS controllers when unimplemented ports were probed
by accident.
Tested on various boards from GM45 to KBL-R.
Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/romcc/romcc.c')
0 files changed, 0 insertions, 0 deletions