diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2017-06-05 13:26:14 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-29 14:59:32 +0000 |
| commit | d39c68a0c034f478cf933bf101d7a62253cc8d02 (patch) | |
| tree | 12cb82955af45f171087b082bfec31cac0347076 /util/romcc/romcc.1 | |
| parent | 028e18ff3caef6976410c2baefbef954b12d92af (diff) | |
soc/intel/cannonlake: Add UART initialization
Cannonlake has built-in UART driver as part of LPSS block. However port
mapped decoders are in use as well.
Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util/romcc/romcc.1')
0 files changed, 0 insertions, 0 deletions