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| author | Subrata Banik <subrata.banik@intel.com> | 2021-09-12 12:23:32 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-09-15 06:21:37 +0000 |
| commit | e58027cc38deb318fb6d6bf1ef1559f44711c452 (patch) | |
| tree | ea67d17733b379213545a49a830562f286a1c34f /util/riscv | |
| parent | cbeeec123c58fcbe33c954e803a06a2aae6c1533 (diff) | |
soc/intel/block/../tcss: Create enum for TCSS Port0/1/2/3
Additionally, convert MAX_TYPE_C_PORTS from macro to enum value.
Change-Id: I3c596d8a015adc0449b44710c6d517753904ecd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions