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author | Angel Pons <th3fanbus@gmail.com> | 2019-01-16 00:18:33 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2019-01-18 19:36:13 +0000 |
commit | 07b6f16063861061da5c14fdd749c85b70848557 (patch) | |
tree | 8beb1b75a823d7edacda09ce12a7fe5902319e66 /util/riscv | |
parent | cd97982e2e2a9eaff50cc9dce02d7d5a18685583 (diff) |
util/autoport: Correct DSDT include statement
With commit aaced4a (cpu/intel/common: Use a common acpi/cpu.asl file),
some model_206ax code was moved to a common place. However, autoport
was not updated accordingly.
Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30967
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions