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author | Huayang Duan <huayang.duan@mediatek.com> | 2020-06-23 13:59:59 +0800 |
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committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-29 14:35:45 +0000 |
commit | 8a02d98c5af8e4a1545ceb72593e3e7561107b79 (patch) | |
tree | 72759f0e2a357263735d04a6dcba4157a40a05e7 /util/riscv | |
parent | 91f74ae16b70872fb63806f7e98122dbf6b3f021 (diff) |
soc/mediatek/mt8192: Implement dramc base settings for each frequency
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I50d5aebaf249ab7292fad7a0046099239c8b403c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions