summaryrefslogtreecommitdiff
path: root/util/riscv
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-17 14:16:03 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-02 21:55:31 +0000
commit717b6e3151b6ea42aaa4b1ab2a708e143d098878 (patch)
treef7caeb3a85a4cc965e62ca5ddf31217751976178 /util/riscv
parent9e69c87317794219d7238eb87edc5e23e03803b4 (diff)
aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INIT
With implementation of LATE_CBMEM_INIT, top-of-low-memory TOLM was adjusted late in ramstage. We do not allow that with EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO space is now used with statically set TOLM. Also remove support code for the obsolete LATE_CBMEM_INIT this northbridge used. Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'util/riscv')
0 files changed, 0 insertions, 0 deletions